Abstract: A high performance pixel is described for active matrix electronic displays. The pixel combines a compact, mesa-isolated PMOS access transistor with a novel, area-efficient HV device. The high voltage transistor features a P+ region at each end of the source to effectively eliminate the parasitic sidewall component and raise the nominal threshold voltage. Concurrently, excess well area is eliminated from the PMOS access transistor to minimize device leakage and the undesirable capacitance component. The improved design enhances pixel response, increases operating margins and contrast and may reduce power dissipation in the off-state.