Abstract: A method and apparatus enable supplementing a Branch Target Buffer (BTB) table with a recent entry queue that prevents unnecessary removal of valuable BTB table data of multiple entries for another entry. The recent entry queue detects when the startup latency of the BTB table prevents it from asynchronously aiding the microprocessor pipeline as designed for and thereby can delay the pipeline in the required situations such that the BTB table latency on startup can be overcome. The recent entry queue provides a quick access to BTB table entries that are accessed in a tight loop pattern where the throughput of the standalone BTB table cannot track the throughput of the microprocessor execution pipeline. By using the recent entry queue, the modified BTB table processes information at the rate of the execution pipeline which provides acceleration thereof.

Abstract: A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

Abstract: A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.

Abstract: A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.

Abstract: A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

Abstract: A mechanism is described that predicts the success or failure of prefetching instructions based on the previous performance of the instructions. A prefetching instruction is successful if the block of information prefetched into the cache is used by the processor before it is discarded from the cache. A prefetching instruction is unsuccessful, a failure, if the block of information prefetched into the cache is not used while in the cache. The prediction regarding the success or failure of the prefetching instruction is performed utilizing a table that records the history regarding the usefulness of each prefetch made by a prefetching instruction at a given memory location. The table is called a Touch-History-Table (THT). The THT is preferably accessed during the decode phase of each instruction using the memory location of the instruction. The table records the history of previous outcomes (success or failure) of the prefetching instruction up to the table size.

Abstract: A operand prefetching mechanism is described for a system having a cache, in addition to its normal memory. The prefetch apparatus utilizes a table that records the location of each instruction that caused an operand miss and the location of the miss. Associated with this information is the address of each instruction fetch block that contains an instruction that caused an operand miss. The table is called an Operand Prefetch Table. With each instruction block fetched from the cache a search is made of the Operand Prefetch table to determine if the instructions found in this block previously caused operand misses. If the instruction block fetched matches an entry in the Operand Prefetch Table then a prefetch for future operands can be attempted for the instructions contained within the instruction block fetch segment.