Patents by Inventor THOMAS ROHLEDER
THOMAS ROHLEDER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847258Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.Type: GrantFiled: September 30, 2015Date of Patent: December 19, 2017Assignee: NXP B.V.Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
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Patent number: 9812361Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.Type: GrantFiled: March 11, 2014Date of Patent: November 7, 2017Assignee: NXP B.V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Martin Lapke, Thomas Rohleder
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Publication number: 20170092540Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
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Patent number: 9601437Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.Type: GrantFiled: September 9, 2014Date of Patent: March 21, 2017Assignee: NXP B.V.Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
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Publication number: 20160172243Abstract: One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and a second device structure having a second location; a material removal controller, coupled to the structures map, and having a material removal beam power level output signal and a material removal beam on/off status output signal; wherein the material removal controller is configured to select a first material removal beam power level and a first material removal beam on/off status corresponding to the first location; and wherein the material removal controller is configured to select a second material removal beam power level and a second material removal beam on/off status corresponding to the second location. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for wafer material removal.Type: ApplicationFiled: December 11, 2014Publication date: June 16, 2016Inventors: Sascha Moeller, Thomas Rohleder, Guido Albermann, Martin Lapke, Hartmut Buenning
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Patent number: 9349645Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.Type: GrantFiled: October 16, 2013Date of Patent: May 24, 2016Assignee: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer
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Publication number: 20160071770Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.Type: ApplicationFiled: September 9, 2014Publication date: March 10, 2016Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
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Publication number: 20150104931Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer
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Publication number: 20150069578Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.Type: ApplicationFiled: March 11, 2014Publication date: March 12, 2015Applicant: NXP B.V.Inventors: Hartmut BUENNING, Sascha MOELLER, Guido ALBERMANN, Martin LAPKE, Thomas ROHLEDER
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Patent number: 8895363Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.Type: GrantFiled: March 15, 2013Date of Patent: November 25, 2014Assignee: NXP B.V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack
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Publication number: 20140264768Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: NXP B. V.Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack
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Patent number: 8809166Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.Type: GrantFiled: December 20, 2012Date of Patent: August 19, 2014Assignee: NXP B.V.Inventors: Hartmut Buenning, Sascha Moeller, Martin Lapke, Guido Albermann, Thomas Rohleder
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Publication number: 20140179083Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NXP B.V.Inventors: HARTMUT BUENNING, SASCHA MOELLER, MARTIN LAPKE, GUIDO ALBERMANN, THOMAS ROHLEDER