Patents by Inventor Thomas Ruane

Thomas Ruane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130004579
    Abstract: The present invention provides compositions and methods for targeting an antigen to leukocytes, delivering an antigen to leukocytes, increasing antigen uptake by leukocytes, and/or enhancing an immune response. In some embodiments, compositions and methods of the present invention comprise a conjugate comprising an antigen and a plant lectin or a mimetic thereof.
    Type: Application
    Filed: May 14, 2012
    Publication date: January 3, 2013
    Inventors: Edward C. Lavelle, Edel McNeela, Darren Thomas Ruane, Christopher Davitt, Karen Misstear
  • Patent number: 7559002
    Abstract: A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Wei-Yi Xiao, Dean Gilbert Bair, Thomas Ruane, William Lewis
  • Patent number: 7509552
    Abstract: A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: March 24, 2009
    Assignee: International Business Machiens Corporation
    Inventors: Wei-Yi Xiao, Dean G. Blair, Thomas Ruane, William Lewis
  • Publication number: 20070255997
    Abstract: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
    Type: Application
    Filed: May 29, 2007
    Publication date: November 1, 2007
    Inventors: Wei-Yi Xiao, Dean Bair, Thomas Ruane, William Lewis
  • Publication number: 20060168497
    Abstract: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Wei-Yi Xiao, Dean Blair, Thomas Ruane, William Lewis