Patents by Inventor Thomas S. ANDRE

Thomas S. ANDRE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with shared amplifier circuitry
    Patent number: 11176974
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 16, 2021
    Assignee: Everspin Technologies Inc.
    Inventors: Syed M. Alam, Thomas S. Andre
  • Delayed write-back in memory
    Patent number: 10657065
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas S. Andre, Syed M. Alam, Chitra K. Subramanian, Javed S. Barkatullah
  • MEMORY DEVICE WITH SHARED AMPLIFIER CIRCUITRY
    Publication number: 20190355398
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas S. ANDRE
  • DELAYED WRITE-BACK IN MEMORY
    Publication number: 20190213136
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas S. ANDRE, Syed M. ALAM, Chitra K. SUBRAMANIAN, Javed S. BARKATULLAH