Patents by Inventor Thomas S. David
Thomas S. David has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10742199Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.Type: GrantFiled: May 20, 2019Date of Patent: August 11, 2020Assignee: Silicon Laboratories Inc.Inventors: Thomas S. David, Wasim Quddus
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Publication number: 20190334507Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.Type: ApplicationFiled: May 20, 2019Publication date: October 31, 2019Inventors: THOMAS S. DAVID, WASIM QUDDUS
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Patent number: 10360104Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.Type: GrantFiled: May 8, 2017Date of Patent: July 23, 2019Assignee: Silicon Laboratories Inc.Inventor: Thomas S. David
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Patent number: 10340894Abstract: A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.Type: GrantFiled: April 26, 2018Date of Patent: July 2, 2019Assignee: Silicon Laboratories Inc.Inventors: Thomas S. David, Wasim Quddus
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Patent number: 10218387Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.Type: GrantFiled: May 8, 2017Date of Patent: February 26, 2019Assignee: Silicon Laboratories Inc.Inventor: Thomas S. David
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Publication number: 20180323808Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventor: Thomas S. David
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Publication number: 20180321875Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventor: Thomas S. David
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Patent number: 9984009Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.Type: GrantFiled: January 28, 2016Date of Patent: May 29, 2018Assignee: SILICON LABORATORIES INC.Inventors: Sebastian Ahmed, Thomas S. David, Marius Grannaes
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Publication number: 20170220489Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: SEBASTIAN AHMED, THOMAS S. DAVID, MARIUS GRANNAES
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Patent number: 9710031Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.Type: GrantFiled: December 30, 2010Date of Patent: July 18, 2017Assignee: Silicon Laboratories Inc.Inventors: Alan L. Westwick, Thomas S. David
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Publication number: 20170139844Abstract: A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.Type: ApplicationFiled: November 17, 2015Publication date: May 18, 2017Applicant: SILICON LABORATORIES INC.Inventors: Paul Ivan Zavalney, Thomas S. David
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Patent number: 9058761Abstract: An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.Type: GrantFiled: June 30, 2009Date of Patent: June 16, 2015Assignee: Silicon Laboratories Inc.Inventors: Douglas Piasecki, Thomas S. David, Timothy Thomas Rueger, Stefan Mastovich, Jia-Hau Liu
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Patent number: 8913051Abstract: An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.Type: GrantFiled: June 30, 2009Date of Patent: December 16, 2014Assignee: Silicon Laboratories Inc.Inventors: Douglas Piasecki, Thomas S. David, Timothy Thomas Rueger, Stefan Mastovich, Jia-Hau Liu
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Patent number: 8825921Abstract: A technique includes executing at least one instruction on a processor to control a driver circuit; and in response to a predetermined trigger condition, asynchronously causing the driver circuit to enter a predetermined state.Type: GrantFiled: December 22, 2010Date of Patent: September 2, 2014Assignee: Silicon Laboratories Inc.Inventors: Alan L. Westwick, Thomas S. David
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Patent number: 8618844Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.Type: GrantFiled: February 24, 2012Date of Patent: December 31, 2013Assignee: Silicon Laboratories Inc.Inventors: Thomas S. David, Paul I. Zavalney
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Publication number: 20130222035Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Inventors: Thomas S. David, Paul I. Zavalney
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Patent number: 8378724Abstract: An apparatus includes a frequency locked loop and a controller. The controller stores a state of the frequency locked loop at which an output signal of the frequency locked loop is locked onto a reference signal and subsequently initializes the frequency locked loop with the stored state to cause the frequency locked loop to relock the output signal to the reference signal.Type: GrantFiled: December 22, 2010Date of Patent: February 19, 2013Assignee: Silicon Laboratories Inc.Inventors: Thomas S. David, Kenneth W. Fernald, Alan L. Westwick
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Patent number: 8274466Abstract: An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad.Type: GrantFiled: March 4, 2009Date of Patent: September 25, 2012Assignee: Silicon Laboratories Inc.Inventors: Thomas S. David, Douglas Piasecki
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Publication number: 20120173787Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Inventors: Alan L. Westwick, Thomas S. David
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Publication number: 20120166859Abstract: An apparatus includes a processor, a clock recovery circuit and a frequency locked loop. The processor receives a system clock signal to clock operations of the processor; and the clock recovery circuit recovers a clock signal from data communication occurring over a bus. The frequency locked loop receives the clock signal from the clock recovery circuit as a reference clock signal, and the frequency locked loop is adapted to lock onto the clock signal provided by the clock recovery circuit to provide the system clock signal.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: Kenneth W. Fernald, Thomas S. David, Alan L. Westwick