Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: Embodiments of the invention include apparatuses and methods relating to conductive interconnects along the edges of a microelectronic device. In one embodiment, the conductive interconnect has the shape of a half cylinder.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: A package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. One or more vias may be formed in one or more trenches. Methods of fabricating an imprinted substrate, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract: A package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract: A diamond micro-channel structure disposed on a die, as well as methods of forming the same, are disclosed. One or more walls of each channel may comprise diamond (or other diamond-like material). The micro-channel structure may form part of a fluid cooling system for the die. Other embodiments are described and claimed.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly depositing a seed layer on the activated non-continuous metal layer and the plurality of non-deposited regions within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free metal filled recess.

Abstract: A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.

Abstract: In some embodiments, an array capacitor for decoupling multiple voltages is presented. In this regard, an array capacitor is introduced having two electrically isolated capacitor regions. Other embodiments are also disclosed and claimed.

Abstract: A package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: Embodiments of the invention include apparatuses and methods relating to conductive interconnects along the edges of a microelectronic device. In one embodiment, the conductive interconnect has the shape of a half cylinder.

Abstract: Some embodiments of the present invention include providing high performance integrated inductors.

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.