Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: A semiconductor substrate has features extending above the surface. In one use, these features are gate stacks in which the gate is polysilicon to be replaced by metal. A dielectric is deposited over the substrate and the gate stacks having contours corresponding to the features. The desired structure prior to replacing the polysilicon gates is for the dielectric to be planar and even with the top of the gate stack. This is difficult to achieve with conventional CMP procedures because of varying polish rates based on the area and density of these features. The desired planarity is achieved by first depositing a conformal sacrificial layer. A CMP step using light downforce results in exposing and planarizing the underlying contours of the dielectric layer. A subsequent CMP step using higher downforce achieves the desired planar structure by providing a greater polish rate for the dielectric layer than for the sacrificial layer.

Abstract: A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Abstract: A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Abstract: In a semiconductor device, a method forms an alternative ground contact for a semiconductor die in which bulk silicon at the back of a die may be electrically grounded to an area containing functional devices and/or to packaging substrate by conductive fillet material surrounding the die and in contact with the bulk silicon and with a guard ring surrounding the area containing functional devices and/or the packaging substrate.

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).

Abstract: A chemical-mechanical polisher (10) includes a mixer section (12) that mixes components of a polishing fluid prior to introducing the polishing fluid into a polishing section (13) of the polisher (10). In one embodiment, components from feed lines (113 and 114) are combined in a manifold (121) and flowed through a static in-line mixer (123) to mix the components to form the polishing fluid. The polishing rate of the polishing fluid is relatively high because the mixing occurs near the point of use. Local concentrations of the components of the polishing fluid near a substrate (134) should be relatively uniform because the polishing fluid is mixed prior to reaching the substrate (134).

Abstract: A chemical-mechanical-polishing (CMP) process in which a metal interconnect material (47) is polished to form a metal plug (48) includes the application of titanium to the surface of a polishing pad (14) of a polishing apparatus (10). Titanium metal is applied to the surface of the polishing pad (14) by either abrasively applying titanium by use of a titanium block (32) attached to a rotating disk (26), or by a titanium body (23, 25) integrated with a carrier ring (23). Alternatively, titanium can be applied by impregnating a felt layer (52) with titanium particles (56), or by adding titanium directly to the polishing slurry (50).

Abstract: A layer over a patterned semiconductor is polished and analyzed to determine a polishing endpoint. The analysis may be performed using reflected radiation beams or by a radiation scattering analyzer. The analysis may be performed on virtually any layer using a radiation source. The analysis may be performed with a liquid, such as an aqueous slurry, contacting the substrate. The polishing and analysis may be integrated such that both steps are performed on the same polisher.

Abstract: A layer over a patterned semiconductor is polished and analyzed to determine a polishing endpoint. The analysis may be performed using reflected radiation beams or by a radiation scattering analyzer. The analysis may be performed on virtually any layer using a radiation source. The analysis may be performed with a liquid, such as an aqueous slurry, contacting the substrate. The polishing and analysis may be integrated such that both steps are performed on the same polisher.

Abstract: A field isolation region is formed by a thermal oxidation followed by a polishing step. In forming the field isolation region, an opening is formed within a nitride layer, but the substrate is not etched. The field isolation region is formed and extends above the opening in the nitride layer. After forming the field isolation region, the substrate is polished, such that the surfaces of the field isolation region and silicon nitride layer are co-planar. The process may be easily integrated into an existing process flow and still provides an integrated circuit having an acceptable field threshold voltage.