Abstract: An embodiment of the invention comprises a method associated with a PCB having a first component, and a second component, that has substantially less thermal mass than the first component. During an initial time period, the PCB and its components are placed at an initial position proximate to a first heat source, which is operable to provide heat energy in accordance with a thermal profile comprising successive phases. After the initial time period, the first heat source is operated during each of the phases in accordance with the thermal profile to selectively apply heat to the PCB and to the plurality of components thereon. During the initial time period or a specified one of the phases, selectively, heat energy from a focused heat source is directed only to the first component, and not to other components.

Abstract: An embodiment of the invention comprises a method associated with a PCB having a first component, and a second component, that has substantially less thermal mass than the first component. During an initial time period, the PCB and its components are placed at an initial position proximate to a first heat source, which is operable to provide heat energy in accordance with a thermal profile comprising successive phases. After the initial time period, the first heat source is operated during each of the phases in accordance with the thermal profile to selectively apply heat to the PCB and to the plurality of components thereon. During the initial time period or a specified one of the phases, selectively, heat energy from a focused heat source is directed only to the first component, and not to other components.

Abstract: A method for clock jitter stress margining of high speed interfaces including generating a jittered clock signal via a clock signal generator of a high speed interface controller card, inputting the jittered clock signal to a control input of a looped-back port of the high speed interface controller card, inputting a test pattern signal to the looped-back port generated from a logic circuitry of the high speed interface controller card, receiving the test pattern signal to the logic circuitry from the looped-back port via the transmitter to the receiver, monitoring a bit error rate of the looped-back port by comparing the received test pattern signal to the inputted test pattern signal, and outputting a fail indication signal if the bit error rate is within a fail threshold.

Abstract: A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface.

Abstract: Systems and methods for managing faults within a high speed network employing wide ports. Exemplary embodiments include a system including a switch module coupled to an end device, the switch device and the end device each have a plurality of PHYs, each of the PHYs on the switch module coupled to a corresponding PHY on the end device, a plurality of wide port cables connected between the switch module and the end device, wherein the coupling of the switch module and the end device defines a wide port, and a process residing on the wide port, the process configured to diagnose faults on the PHYs and having instructions to identify an operational PHY, instruct the operational PHY to take command over the remaining PHYs in the wide port, execute diagnostic sub-routines within the port to identify failed PHYs and report diagnostic data to the operational PHY.

Abstract: Systems and methods for diagnosing faults in a multiple domain storage system. Exemplary embodiments include a system for diagnosing faults, the system including independent servers coupled to a serial attached SCSI switch module, end devices coupled to the serial attached SCSI module, at least one external cable connected between the serial attached SCSI module and the plurality of end devices, wherein the external cable defined an external fabric between the serial attached SCSI module and the plurality of end devices; and a process residing on the external fabric, the process having instructions to disable a high speed serializer/deserializer residing on each of the plurality of end devices, enable a universal asynchronous receiver/transmitter interface residing on each of the plurality of end devices, send and receive single ended data and in response to a complete data transfer, disabling the universal asynchronous receiver/transmitter interface and enabling the high speed serializer/deserializer.