Abstract: A method used by an electronic design automation system for partitioning the logic design of an integrated circuit and generating test patterns for testing the integrated circuit. The logic design of the integrated circuit includes a gate-level description having components and nets. Nets include base nets input to the integrated circuit and apex nets output from the integrated circuit. The nets are specified by vector net notation. The method includes creating a plurality of cones of logic design from the logic design of the integrated circuit. Each cone is defined by tracing a path from an apex net, defined by a logic designer, output from a logical register of the logic design to a logic designer-defined base net affecting the logical register. A test pattern is then automatically generated for each of the traced cones of logic design.

Abstract: Mutually Exclusive Gating (MEG) requirements arising from the use of level Sensitive Scan Design (LSSD) rules are satisfied for handling clock phase conflicts in an integrated circuit design. Automatic generation of test patterns for hardware testing of a manufactured integrated circuit is completed without adding logic to the integrated circuit's design. The automatic test pattern generation (ATPG) system identifies and traces cones of logic from a detailed description of an integrated circuit's design. The system also identifies portions of cones that are functional data, clock, and enable input nets. Multiple cones are grouped into partitions. During partitioning, input latches of a cone being driven by the same functional clock as an apex latch of the cone are identified. A net list is created for each partition.