Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Abstract: In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.

Abstract: A data synchronizer including an input stage, a driver stage, and a keeper stage. The input stage latches input data to a data node in response to a first clock signal transition. The driver stage has an input coupled to the data node and has an output coupled to a gain node. The keeper stage latches data asserted on the gain node back to the input stage to maintain data on the data node in response to a second transition of the clock signal. The driver stage has an increased drive strength and a reduced loading capacitance to increase the gain-bandwidth product of the latch loop to reduce metastability. A flip-flop may be configured with input and output latches each including driver stages having increased drive strength and reduced loading capacitance to increase the gain-bandwidth product of each of the latch loops to reduce metastability.

Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.

Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.

Abstract: An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.

Abstract: A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Abstract: An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.

Abstract: In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.

Abstract: In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.

Abstract: An apparatus comprises a source to communicate data, and a storage circuit to store data communicated by the source. The apparatus further comprises a write-back buffer to store data communicated by the source in a misaligned write operation in order to improve throughput between the source and the storage circuit.

Abstract: An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.

Abstract: An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.

Abstract: A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Abstract: An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.

Abstract: A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.