Patents by Inventor Thomas Savell

Thomas Savell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170039477
    Abstract: In an inference engine a conditional dependency of variables is characterized in terms of second order uncertainty to aid in improving decision making speed and precision. Mean and distribution of evidence states are utilized to provide first order uncertainties for each of a plurality of states. Higher order statistics such as standard deviation and variance for the states are calculated in order to define second order uncertainties. A covariance layer of the inference engine receives variance information from parent nodes for calculating the states of a child node. Second order uncertainty expresses conditional dependency of the parameters to which the child node responds. The method and apparatus are generalized to apply the propagation of second order uncertainty through inference engines such as Bayesian Networks, Influence Diagrams and Probabilistic Relational Models, to output control signals.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 9, 2017
    Inventor: C. Thomas Savell
  • Publication number: 20070162706
    Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 12, 2007
    Inventors: Thomas Savell, Carl Wakeland
  • Publication number: 20060133628
    Abstract: MIDI-generated audio streams or other input streams of audio events are perceptually associated with specific locations in 3D space with respect to the listener. A conventional pan parameter is redefined so that it no longer specifies the relative balance between the audio being fed to two fixed speaker locations. Instead, the new MIDI pan parameter extension specifies a virtual position of an audio stream in 3D space. Preferably, the relative position of a single audio stream is set along a predefined arc in 3D space.
    Type: Application
    Filed: December 1, 2005
    Publication date: June 22, 2006
    Inventors: Jean-Michel Trivi, Jean-Marc Jot, Thomas Savell, Michael Guzewicz
  • Publication number: 20050289298
    Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Inventors: Thomas Savell, Carl Wakeland
  • Publication number: 20050033586
    Abstract: A digital processing device to process media data is provided. The device includes a plurality of processing modules to process the media data, and a media data path. The media data path communicates the media data between the processing modules, wherein the media data path is arranged in a ring configuration. In one embodiment, the media data path defines a digital audio bus that serially interconnects the plurality of processing modules. The digital audio bus may communicate digital audio data in a plurality of time-slots, each particular processing module having an associated time-slot from which data is received from the data path for processing by the particular processing module.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 10, 2005
    Inventor: Thomas Savell