Abstract: A pattern generator employs a delay-locked loop (DLL) to generate a control signal for locking a delay though each element in a reference generator string to a reference signal. The control signal is also employed to lock a delay though each element in a pattern generator string to the reference signal. The elements may be slew-rate-controlled inverters, where the DLL control signal adjusts the slewing-rate of the inverter. Given a signal applied to the pattern generator string, combination logic assembles one or more pulses from the two or more signals selected from the input and output taps of each of the series of elements in the pattern generator string. Since the delay through each element of the series of elements in the pattern generator string is locked, the period of each pulse may exhibit relatively accurate timing with respect to the reference.