Abstract: A syringe configured with a limited maximum usable capacity. The syringe of the invention desirably has a retractable needle to prevent reuse. In the preferred embodiment, a dose-limiting structure includes a stop-ring member on the head of the plunger that abuts a constriction in the housing when the plunger is moved away from the needle to prevent the further rearward movement of the plunger. Preferably, the syringe of the invention is configured such that a user is tactilely signaled when the plunger has reached a position corresponding to a nominal fixed-dose. If the user attempts to force the stop-ring member beyond the constriction, the plunger seal is stripped off or removed from the plunger head and the syringe rendered inoperable. The features of the invention can also be applied to a nonretracting syringe.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.

Abstract: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.

Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

Abstract: Test tool logic and testing methods are provided for facilitating testing a duplexed computer function, such as a duplexed coupling facility. The test tool allows a testcase written for a first environment to be automatically driven in a second environment, thereby facilitating testing of a function of the second environment. Other aspects include logic for intercepting a system event by a test tool to facilitate testing of system-managed event processing, and for adjusting a display characteristic of one or more messages to be displayed by the test tool based on message type. Further, logic for propagating an environmental error indication and for facilitating processing a wait state are also provided, as are several new test tool verbs and macros.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

Abstract: Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

Abstract: A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.

Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

Abstract: An IV catheter introducer having a retractable needle holder and a tubular plunger that are held by a detent structure in a preferred positional relationship prior to and during insertion of the catheter. Following insertion, the plunger is pushed past the detent structure, permitting a compressed spring to force the needle holder upwardly into the plunger. A vented end cap in the plunger permits rapid venting of air displaced during retraction of the needle holder. The needle holder includes a flash chamber that is easily viewable through a clear plastic housing. Wings are provided on the housing to facilitate one-handed operation of the device. A method for assembling the subject catheter introducer is also disclosed.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

Abstract: A high pressure cryogenic fluid dispensing system features a tank containing a cryogenic liquid with a liquid side and a head space there above. A pressure building coil featuring a section of parallel heat exchangers and a section of series heat exchangers receives liquid from the tank through a pressure building regulator valve and a pair of surge check valves. The liquid flashes to gas in the section of parallel heat exchangers and the resulting gas is forced to the section of series heat exchangers where it is pressurized and warmed. The gas may be directed to a warming coil for dispensing and to the head space of the tank to rapidly pressurize it. Gas traveling to the head space flows through an vapor space withdrawal control valve. The vapor space withdrawal control valve and pressure building regulator valve may be automated via a controller that provides pressure building when the tank pressure drops below the system operating pressure.

Abstract: A color changing apparatus adapted to be installed between the reflector assembly and front barrel assembly of a theatrical ellipsoidal spotlight. The color changing apparatus includes a housing for connecting to the spotlight components. Contained within the housing are a plurality of color filters, preferably dichroic color filters, serially arranged perpendicular to the light path. The color filters may include constant or variable density patterns of any desirable color and are transported into the light path to effect a change in lighting conditions. The color changing apparatus is also preferably equipped with a control system enabling remote actuation and control of the system.

Abstract: A color changing apparatus adapted to be installed between the reflector assembly and front barrel assembly of a theatrical ellipsoidal spotlight. The color changing apparatus includes a housing for connecting to the spotlight components. Contained within the housing are a plurality of color filters, preferably dichroic color filters, serially arranged perpendicular to the light path. The color filters may include constant or variable density patterns of any desirable color and are transported into the light path to effect a change in lighting conditions. The color changing apparatus is also preferably equipped with a control system enabling remote actuation and control of the system.

Abstract: A high pressure cryogenic fluid dispensing system features a tank containing a cryogenic liquid with a liquid side and a head space there above. A pressure building coil featuring a section of parallel heat exchangers and a section of series heat exchangers receives liquid from the tank through a pressure building regulator valve and a pair of surge check valves. The liquid flashes to gas in the section of parallel heat exchangers and the resulting gas is forced to the section of series heat exchangers where it is pressurized and warmed. The gas may be directed to a warming coil for dispensing and to the head space of the tank to rapidly pressurize it. Gas traveling to the head space flows through an vapor space withdrawal control valve. The vapor space withdrawal control valve and pressure building regulator valve may be automated via a controller that provides pressure building when the tank pressure drops below the system operating pressure.