Abstract: An input/output buffer for computer circuitry including a P type transistor device responsive to data signals for selectively furnishing voltage from a first source of potential at a buffer input/output terminal, a first predriver circuit for furnishing data signals from a source to the P type transistor device, the first predriver circuit including circuitry for slowing the application of data signals to the P type transistor device when the buffer input/output terminal is at a high level, a N type transistor device responsive to data signals for selectively furnishing voltage from a second source of potential at the buffer output terminal, a second predriver circuit for furnishing data signals from the source to the N type transistor device, and circuitry for slowing the receipt of data signals at the first predriver circuit.