Patents by Inventor Thomas Sounart
Thomas Sounart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063091Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
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Publication number: 20240063202Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Thomas Sounart, Henning Braunisch, William J. Lambert, Kaladhar Radhakrishnan, Shawna M. Liff, Mohammad Enamul Kabir, Omkar G. Karhade, Kimin Jun, Johanna M. Swan
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Patent number: 11908687Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.Type: GrantFiled: December 28, 2021Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Khaled Ahmed, Anup Pancholi, John Heck, Thomas Sounart, Harel Frish, Sansaptak Dasgupta
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Publication number: 20240014149Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.Type: ApplicationFiled: September 25, 2023Publication date: January 11, 2024Inventors: Aleksandar ALEKSOV, Thomas SOUNART, Kristof DARMAWIKARTA, Henning BRAUNISCH, Prithwish CHATTERJEE, Andrew J. BROWN
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Publication number: 20230402499Abstract: Capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such capacitors include a transition metal oxide dielectric between two electrodes, at least one of which includes a conductive metal oxide layer on the transition metal oxide dielectric and a high density metal layer on the conductive metal oxide.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Tristan Tronic
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Patent number: 11804455Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.Type: GrantFiled: October 4, 2022Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Thomas Sounart, Kristof Darmawikarta, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown
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Patent number: 11756948Abstract: Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.Type: GrantFiled: May 1, 2019Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Thomas Sounart, Aleksandar Aleksov, Henning Braunisch
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Publication number: 20220392855Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Benjamin T. Duong, Srinivas V. Pietambaram, Thomas Sounart, Aleksandar Aleksov, Adel A. Elsherbini
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Patent number: 11495552Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.Type: GrantFiled: June 29, 2018Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Thomas Sounart, Kristof Darmawikarta, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown
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Publication number: 20220122842Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.Type: ApplicationFiled: December 28, 2021Publication date: April 21, 2022Applicant: Intel CorporationInventors: Khaled Ahmed, Anup Pancholi, John Heck, Thomas Sounart, Harel Frish, Sansaptak Dasgupta
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Patent number: 11302618Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.Type: GrantFiled: April 9, 2018Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Feras Eid, Shawna M. Liff, Thomas Sounart, Johanna M. Swan
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Publication number: 20220102483Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Aleksandar Aleksov, Henning Braunisch, I-Cheng Tung
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Patent number: 11211245Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.Type: GrantFiled: June 2, 2020Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Khaled Ahmed, Anup Pancholi, John Heck, Thomas Sounart, Harel Frish, Sansaptak Dasgupta
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Publication number: 20210375620Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.Type: ApplicationFiled: June 2, 2020Publication date: December 2, 2021Applicant: Intel CorporationInventors: Khaled Ahmed, Anup Pancholi, John Heck, Thomas Sounart, Harel Frish, Sansaptak Dasgupta
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Publication number: 20200350303Abstract: Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.Type: ApplicationFiled: May 1, 2019Publication date: November 5, 2020Inventors: Thomas SOUNART, Aleksandar ALEKSOV, Henning BRAUNISCH
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Publication number: 20200126921Abstract: Electronics package device technology is disclosed. In one example, an electronics package device (202) comprises substrate (206) supporting an electronics component (208) and an interconnect via (216a-c) electrically coupled to the electronics component such that at least a portion of the electronics component is disposed between the interconnect via and the substrate. The interconnect via can be directly coupled to the electronics component such that the interconnect via and the electronics component are vertically disposed between a second electronics package device (204) and the substrate. A second electronics package device can be stacked to the first electronics package device, and can comprise similar architecture of the interconnect via attached to the electronics component as with the first electronics package. Thus, 3D package size is significantly reduced. Associated systems and processes are disclosed.Type: ApplicationFiled: April 1, 2017Publication date: April 23, 2020Applicant: Intel CorporationInventors: Vijay K. Nair, Feras Eid, Thomas Sounart
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Publication number: 20200006258Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Aleksandar ALEKSOV, Thomas SOUNART, Kristof DARMAWIKARTA, Henning BRAUNISCH, Prithwish CHATTERJEE, Andrew J. BROWN
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Publication number: 20190311980Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Applicant: Intel CorporationInventors: Feras Eid, Shawna M. Liff, Thomas Sounart, Johanna M. Swan