Patents by Inventor Thomas Sounart

Thomas Sounart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12374626
    Abstract: Electronics package device technology is disclosed. In one example, an electronics package device (202) comprises substrate (206) supporting an electronics component (208) and an interconnect via (216a-c) electrically coupled to the electronics component such that at least a portion of the electronics component is disposed between the interconnect via and the substrate. The interconnect via can be directly coupled to the electronics component such that the interconnect via and the electronics component are vertically disposed between a second electronics package device (204) and the substrate. A second electronics package device can be stacked to the first electronics package device, and can comprise similar architecture of the interconnect via attached to the electronics component as with the first electronics package. Thus, 3D package size is significantly reduced. Associated systems and processes are disclosed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: July 29, 2025
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Feras Eid, Thomas Sounart
  • Publication number: 20250218847
    Abstract: A first carrier comprises a plurality of regions. Each region comprises a first zone and a second zone. The second zone comprises a portion that surrounds the first zone. Each first zone comprises a hydrophilic surface, and each second zone comprises a hydrophobic surface. A first liquid is deposited on the first carrier. The plurality of regions are aligned with a plurality of dies on a second carrier. The dies are transferred from the second carrier to the first carrier. A second liquid is deposited on a substrate, which includes a plurality of bond areas. Each die bond area comprises a hydrophilic surface. The dies are transferred from the first carrier to the substrate.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Veronica A. Strong, Feras Eid, Chien-An Chen, Wenhao Li, Bhaskar Jyoti Krishnatreya, Thomas Sounart, Adel Elsherbini, Kimin Jun, Johanna Swan
  • Publication number: 20250210392
    Abstract: Various aspects may provide a handling assembly. The handling assembly may include a body with a component-handling surface. The component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. The handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. In the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Bhaskar Jyoti KRISHNATREYA, Michael J. BAKER, Feras EID, Wenhao LI, Veronica STRONG, Thomas SOUNART, Adel A. ELSHERBINI, Johanna M. SWAN, Kimin JUN, Yi SHI, Xavier BRUN, Shawna M. LIFF, Edison Chien-An CHEN
  • Publication number: 20250192096
    Abstract: A system that includes a self-assembly module and a bonding module. The self-assembly module has a liquid dispensing unit, with an applicator and a reservoir for a liquid, that dispenses the liquid onto a wafer, a wafer support, an environmental control unit, a die and wafer transport mechanism, and a processor. A method for performing the hybrid bonding includes providing a wafer, patterning the wafer to form a hydrophobic surface with a plurality of hydrophilic regions, disposing the wafer on the wafer support in the self-assembly module of the hybrid bonding system, dispensing the liquid simultaneously or in batches on the plurality of hydrophilic regions on the wafer, positioning dies on the plurality of hydrophilic regions on the wafer, controlling the humidity and bonding the dies to the wafer using a hybrid bonding process.
    Type: Application
    Filed: December 11, 2023
    Publication date: June 12, 2025
    Inventors: Yi SHI, Thomas SOUNART, Michael BAKER, Seyed Hadi ZANDAVI, Feras EID, Adel A. ELSHERBINI
  • Publication number: 20250112185
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Thomas Sounart, Michael Baker, Seyed Hadi Zandavi, Yi Shi, Feras Eid
  • Publication number: 20250112173
    Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Thomas Sounart, Yi Shi, Wenhao Li
  • Publication number: 20250112181
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Yi Shi, Kimin Jun, Adel Elsherbini, Thomas Sounart, Wenhao Li, Xavier Brun
  • Publication number: 20250112200
    Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Kimin Jun, Feras Eid, Thomas Sounart, Yi Shi, Shawna Liff, Johanna Swan, Michael Baker, Bhaskar Jyoti Krishnatreya, Chien-An Chen
  • Publication number: 20250112187
    Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Thomas Sounart, YI Shi
  • Publication number: 20250112186
    Abstract: A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Thomas Sounart, Kimin Jun, Wenhao Li
  • Publication number: 20250112127
    Abstract: A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding process a biphilic surface on the IC die structure or substrate structure may facilitate liquid droplet-based fine alignment of the IC die structure to a host structure. Prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Veronica Strong, Thomas Sounart
  • Publication number: 20250112155
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Scott Clendenning, Feras Eid, Robert Jordan, Wenhao Li, Jiun-Ruey Chen, Tayseer Mahdi, Carlos Felipe Bedoya Arroyave, Shashi Bhushan Sinha, Anandi Roy, Tristan Tronic, Dominique Adams, William Brezinski, Richard Vreeland, Thomas Sounart, Brian Barley, Jeffery Bielefeld
  • Publication number: 20250112177
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Thomas Sounart, Yi Shi, Michael Baker, Adel Elsherbini, Kimin Jun, Xavier Brun, Wenhao Li
  • Publication number: 20250112199
    Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Thomas Sounart, Feras Eid, Adel Elsherbini, Yi Shi, Michael Baker, Kimin Jun, Wenhao Li
  • Patent number: 12255225
    Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Aleksandar Aleksov, Henning Braunisch, I-Cheng Tung
  • Publication number: 20250006781
    Abstract: Carbon nanofiber capacitor apparatus and related methods are disclosed herein. An example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. The capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Thomas Sounart, Henning Braunisch, Aleksandar Aleksov, Kristof Darmawikarta, Darko Grujicic, Marcel Wall, Suddhasattwa Nad, Benjamin Duong, Shayan Kaviani
  • Publication number: 20240222018
    Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Thomas Sounart, Henning Braunisch, Aleksandar Aleksov, Kristof Darmawikarta, Numair Ahmed, Darko Grujicic, Suddhasattwa Nad, Benjamin Duong, Marcel Wall, Shayan Kaviani
  • Publication number: 20240222035
    Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Kristof Darmawikarta, Benjamin Duong, Gang Duan, Srinivas Pietambaram, Brandon Marin, Jeremy Ecton, Jason Steill, Thomas Sounart, Darko Grujicic
  • Publication number: 20240063091
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
  • Publication number: 20240063202
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Thomas Sounart, Henning Braunisch, William J. Lambert, Kaladhar Radhakrishnan, Shawna M. Liff, Mohammad Enamul Kabir, Omkar G. Karhade, Kimin Jun, Johanna M. Swan