Patents by Inventor Thomas Stephen Chanak, Jr.

Thomas Stephen Chanak, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof
    Patent number: 8291364
    Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 16, 2012
    Assignee: MIPS Technologies, Inc.
    Inventors: Avishek Panigrahi, Soumya Banerjee, Thomas Stephen Chanak, Jr.
  • Automated Digital Circuit Design Tool That Reduces or Eliminates Adverse Timing Constraints Due To An Inherent Clock Signal Skew, and Applications Thereof
    Publication number: 20110138349
    Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Applicant: MIPS Technologies, Inc.
    Inventors: Avishek PANIGRAHI, Soumya Banerjee, Thomas Stephen Chanak, JR.
  • Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
    Patent number: 7917882
    Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: March 29, 2011
    Assignee: MIPS Technologies, Inc.
    Inventors: Avishek Panigrahi, Soumya Banerjee, Thomas Stephen Chanak, Jr.
  • Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
    Publication number: 20090113365
    Abstract: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Applicant: MIPS Technologies, Inc.
    Inventors: Avishek Panigrahi, Soumya Banerjee, Thomas Stephen Chanak, JR.