Patents by Inventor Thomas STETTNER

Thomas STETTNER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186168
    Abstract: A process produces semiconductor wafers with epitaxial layer deposited from a gas phase in a deposition chamber. The process includes placing a substrate wafer on a susceptor with circular perimeter by a robot that moves the substrate wafer into a placement position and places it on the susceptor with a corrective precept causing a center of the substrate wafer not to lie above a center of the susceptor; and depositing the epitaxial layer on the substrate wafer. A first number of substrate wafers having a specific resistance which falls within a first range are moved into the placement position with a first corrective precept, and a second number of substrate wafers having a specific resistance which falls within a second range are moved by the robot with a second corrective precept, differs from the first corrective precept.
    Type: Application
    Filed: March 31, 2022
    Publication date: June 6, 2024
    Inventor: Thomas Stettner
  • Publication number: 20240117523
    Abstract: Disclosed is a process for manufacturing semiconductor wafers containing a gas-phase epitaxial layer in a deposition chamber, involving removing, from the deposition chamber by etching the deposition chamber, material settled in the deposition chamber during preceding coating processes; performing successive coating operations in the etched deposition chamber, each of said coating operations involving having a robot place a substrate wafer on a susceptor having a circular circumference, the robot moving the substrate wafer into a drop-off position and placing it on the susceptor, the center of the substrate wafer not lying over the center of the susceptor in the drop-off position because of a predefined corrective parameter; and depositing an epitaxial layer on the substrate wafer such that a semiconductor wafer containing an epitaxial layer is produced, characterized in that for each first substrate wafer moved by the robot into the drop-off position, the value of the predefined corrective parameter correspo
    Type: Application
    Filed: March 28, 2022
    Publication date: April 11, 2024
    Inventor: Thomas Stettner
  • Publication number: 20240021449
    Abstract: A characteristic thickness value of an edge of a wafer is determined, including at a notch position. The wafer is placed in a placement area, surrounded by a boundary, of susceptor for depositing an epitaxial layer. The characteristic thickness value at the notch position is checked to see if it differs by more than a percentage limit from the characteristic thickness value at an edge position having the greatest characteristic thickness value. The placing of the substrate wafer on the placement area is executed in such a way that a distance of the wafer from the boundary of the placement area is smaller at the edge position having the greatest characteristic thickness value or at the notch position than at other edge positions.
    Type: Application
    Filed: October 27, 2021
    Publication date: January 18, 2024
    Inventor: Thomas Stettner
  • Publication number: 20230366095
    Abstract: A method deposits an epitaxial layer on a semiconductor substrate having a wedge-shaped cross section. The substrate is arranged in a deposition apparatus to rest concentrically on a susceptor held by a supporting shaft. The supporting shaft rotates with a time period. Deposition gas is passed over the substrate between a gas inlet and outlet. Flushing gas is passed along a lower side of a preheating ring and of the susceptor. The supporting shaft is displaced with the time period along a displacement path from a position where a thinner edge of the substrate has its smallest distance from the gas inlet, to where the thinner edge has its largest distance therefrom, and back.
    Type: Application
    Filed: September 20, 2021
    Publication date: November 16, 2023
    Inventors: Thomas Stettner, Walter Edmaier
  • Publication number: 20230265581
    Abstract: An epitaxial layer is deposited on a substrate wafer by a method including measuring an edge geometry of the wafer, placing the wafer at a position in a pocket of a susceptor of a device for depositing the layer based on the edge geometry, heating the wafer, and passing a process gas over the wafer. Thickness characteristic values are assigned to edge portions based on the edge geometry. The position in the pocket is determined as function of an expected change in the thickness characteristic value to an eccentricity E, which is determined by prior testing of the device. The function is a result of the shape of the pocket which has a boundary having a circular circumference. The distance from the wafer to the boundary of the pocket is less at thicker edge portions and greater at thinner edge portion so the layer has thicknesses inverse to the wafer thicknesses.
    Type: Application
    Filed: July 21, 2021
    Publication date: August 24, 2023
    Applicant: SILTRONIC AG
    Inventors: Thomas STETTNER, Martin WENGBAUER
  • Publication number: 20230178398
    Abstract: A method and an apparatus for depositing an epitaxial layer on a substrate wafer made of semiconductor material. The method comprises the arrangement of the substrate wafer and a susceptor in a deposition device such that the substrate wafer rests on the susceptor and the susceptor is held by arms of a support shaft; monitoring whether a misalignment of the susceptor exists with respect to its position relative to the position of a pre-heating ring surrounding it; monitoring whether a misalignment of the support shaft exists with respect to its position relative to the position of the pre-heating ring; if at least one of the misalignments is present, elimination of the respective misalignment; and the deposition of the epitaxial layer on the substrate wafer.
    Type: Application
    Filed: April 14, 2021
    Publication date: June 8, 2023
    Applicant: SILTRONIC AG
    Inventors: Thomas STETTNER, Walter EDMAIER, Korbinian LICHTENEGGER, Hannes HECHT