Patents by Inventor Thomas Stoek

Thomas Stoek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901257
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Michael Stadler
  • Patent number: 11862541
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11769748
    Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Michael Stadler, Mohd Hasrul Zulkifli
  • Publication number: 20230282553
    Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/?30 ?m at the first side of the power module.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Thomas Stoek, Frank Daeche, Chee Voon Tan
  • Patent number: 11699640
    Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/?30 ?m at the first side of the power module.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Frank Daeche, Chee Voon Tan
  • Patent number: 11621204
    Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: April 4, 2023
    Assignee: Infineon Technologies AG
    Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
  • Publication number: 20230094794
    Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 30, 2023
    Inventors: Thomas Stoek, Michael Stadler, Mohd Hasrul Zulkifli
  • Patent number: 11545459
    Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Michael Stadler, Mohd Hasrul Zulkifli
  • Publication number: 20220406692
    Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/?30 ?m at the first side of the power module.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Inventors: Thomas Stoek, Frank Daeche, Chee Voon Tan
  • Publication number: 20220262693
    Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
  • Publication number: 20220238475
    Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Inventors: Thomas Stoek, Michael Stadler, Mohd Hasrul Zulkifli
  • Publication number: 20220189855
    Abstract: An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Infineon Technologies AG
    Inventors: Christian FEUERBAUM, Thomas STOEK
  • Publication number: 20220115245
    Abstract: A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 14, 2022
    Inventors: Jayaganasan Narayanasamy, Syahir Abd Hamid, Meng How Chong, Michael Reyes Godoy, Chee Ming Lam, Adbul Rahman Mohamed, Sanjay Kumar Murugan, Thomas Stoek
  • Patent number: 11302613
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Patent number: 11183445
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Daeche, Daniel Schleisser, Thomas Stoek
  • Publication number: 20210358836
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11101201
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 10971436
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Publication number: 20210020547
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Publication number: 20210020550
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan