Patents by Inventor Thomas Stoek

Thomas Stoek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183445
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Daeche, Daniel Schleisser, Thomas Stoek
  • Publication number: 20210358836
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11101201
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 10971436
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Publication number: 20210020547
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Publication number: 20210020550
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 21, 2021
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Patent number: 10886199
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 5, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Publication number: 20200279795
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Publication number: 20200279799
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Application
    Filed: January 29, 2020
    Publication date: September 3, 2020
    Inventors: Dirk AHLERS, Frank DAECHE, Daniel SCHLEISSER, Thomas STOEK
  • Publication number: 20200185301
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventors: Thomas Stoek, Michael Stadler
  • Patent number: 10651109
    Abstract: A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Syahir Abd Hamid, Jagen Krishnan, Mian Mian Lam, Jayaganasan Narayanasamy, Fabian Schnoy, Thomas Stoek, Christian Stuempfl
  • Publication number: 20200020618
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 16, 2020
    Inventors: Thomas STOEK, Chii Shang HONG, Chiew Li TAI, Edmund Sales CABATBAT
  • Publication number: 20200020607
    Abstract: A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 16, 2020
    Inventors: Syahir Abd Hamid, Jagen Krishnan, Mian Mian Lam, Jayaganasan Narayanasamy, Fabian Schnoy, Thomas Stoek, Christian Stuempfl
  • Patent number: 10354943
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Patent number: 10319671
    Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Patent number: 10147703
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Publication number: 20180342438
    Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoek, Gilles Delarozee
  • Publication number: 20180342447
    Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 29, 2018
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Publication number: 20180277513
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Patent number: 9978672
    Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek