Patents by Inventor Thomas Strach

Thomas Strach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734317
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 10725517
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Publication number: 20200201407
    Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
  • Publication number: 20200201413
    Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
  • Publication number: 20200033927
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Application
    Filed: October 8, 2019
    Publication date: January 30, 2020
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Patent number: 10481662
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Patent number: 10461715
    Abstract: Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Bernhard Schmidt, Thomas Strach, Hubert Harrer, Jochen Supper
  • Publication number: 20190295938
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 10354946
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 10149388
    Abstract: A method for embedding a discrete electrical device in a printed circuit board (PCB) is provided, which includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to a conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first device contact and the conductive structure in the first layer; and establishing a second electrical connection between a second device contact and a second layer, the second layer being one of the conductive layers of a second horizontal core section.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES, CORPORATION
    Inventors: Bruce J. Chamberlin, Andreas Huber, Harald Huels, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 10145892
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 4, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMPUTER TASK GROUP, INC.
    Inventors: Robert L. Franch, Phillip J. Restle, Thomas Strach, Christos Vezyrtzis, Scott F. Warnock
  • Patent number: 10114914
    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Publication number: 20180228028
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 9980385
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 22, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Publication number: 20180107771
    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.
    Type: Application
    Filed: November 28, 2017
    Publication date: April 19, 2018
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Publication number: 20180088650
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 29, 2018
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Patent number: 9904748
    Abstract: A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Publication number: 20180052200
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: ROBERT L. FRANCH, PHILLIP J. RESTLE, THOMAS STRACH, CHRISTOS VEZYRTZIS, SCOTT F. WARNOCK
  • Publication number: 20180027659
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Application
    Filed: April 24, 2017
    Publication date: January 25, 2018
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 9839131
    Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce J. Chamberlin, Andreas Huber, Harald Huels, Thomas Strach, Thomas-Michael Winkel