Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device.

Abstract: An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four memory arrays for storing data. The first and third memory arrays are operable to simultaneously output an integer even number E of data values. The second and fourth memory arrays are operable to simultaneously output an integer odd number D of data values. The integrated circuit further includes circuitry for selectively coupling the first, second, third, and fourth memory arrays to the electrical contacts, wherein the circuitry for selectively coupling is operable to couple the first and fourth memory arrays to the electrical contacts in a first state so that the first memory array outputs E data values and the fourth memory array outputs D data values in the first state.

Abstract: According to the present invention, a method and structure for using pre-charged data path techniques in those applications where it is necessary to retain the previous state of data is presented. In the preferred embodiment, a Pre-Charged Slave Latch with Parallel Previous State Memory circuit of a burst SRAM employs a parallel memory element configuration. In conjunction with this parallel memory element configuration, three stages are disclosed to implement a pre-charged data path technique for a burst SRAM memory. First, external data is loaded into the Pre-Charged Slave Latch with Parallel Previous State Memory circuit. Next, during a burst address sequence state of the Burst SRAM, the previous address state is allowed to propagate through the address decode path of the burst SRAM. Finally, the output signal of the Pre-Charged Slave Latch with Parallel Previous State Memory is pre-charged to an inactive state in parallel with other circuit elements of the pre-charged address decode path.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A memory and a method involving the memory. The memory includes a memory array having a data quantity output for outputting a data quantity and a data output driver having an input for receiving the data quantity and an output for outputting the data quantity from the memory. The memory further includes a data quantity pipeline register having an input for receiving the data quantity and an output coupled to the input of the data output driver. Finally, the memory includes means for selectively coupling a data quantity from the data output of the memory array to the input of the data output driver in a first operational mode and to the input of the data quantity pipeline register in a second operational mode.

Abstract: A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell to an address of a defective memory column. An enable line communicates with the redundant memory column and selectively carries active and inactive signal levels for respectively enabling and disabling communication between the data bus and the redundant memory cell. An address decoder receives an address signal on the address bus and generates the active level on the enable line when the value of the address signal equals the address of the defective memory cell. A driver precharges the enable line to the inactive level while the address signal is invalid.

Abstract: An apparatus maps one of a plurality of redundant memory columns, each having a redundant memory cell, to an address of a defective memory column in a memory device that communicates with an external data bus having one or more data-bit lines and an address bus. An address decoder receives an address signal on the address bus and generates an enable signal to enable the redundant cell of the redundant column when the value of the address signal equals the address of the defective memory column. A bit-select bus has one or more bit-select lines each associated with one of the data-bit lines. Each bit-select line can carry a bit-select signal. Each of a plurality of bit-line selectors is associated with one of the redundant columns and communicates with the bit-select bus. In response to an associated enable signal, each bit-line selector can generate the bit-select signal on the bit-select line associated with a desired data-bit line.

Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device.

Abstract: The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.

Abstract: Therefore, according to the present invention, replacement of defective elements of an integrated circuit memory device by a redundant array is accomplished using a redundant decode scheme which is as fast as or faster than the standard decode. An exclusionary wired-connection redundant select circuit, which is programmable and pre-charged, allows the redundant array to be programmed such that any defective element may be replaced in a quick manner. The exclusionary wired-connection redundant select circuit is enabled by programming a programmable element of an enable circuit contained within the exclusionary wired-connection redundant select circuit and is programmed by disconnecting all programmable elements of the select circuit not representative of the defective element to be replaced. The output signal of the exclusionary wired-connection redundant select circuit propagates to decode output slave latch circuitry where it is latched and stored.

Abstract: According to the present invention, a method and structure for using precharged data path techniques in those applications where it is necessary to retain the previous state of data is presented. In the preferred embodiment, a Pre-Charged Slave Latch with Parallel Previous State Memory circuit of a burst SRAM employs a parallel memory element configuration. In conjunction with this parallel memory element configuration, three stages are disclosed to implement a pre-charged data path technique for a burst SRAM memory. First, external data is loaded into the Pre-Charged Slave Latch with Parallel Previous State Memory circuit. Next, during a burst address sequence state of the Burst SRAM, the previous address state is allowed to propagate through the address decode path of the burst SRAM. Finally, the output signal of the Pre-Charged Slave Latch with Parallel Previous State Memory is precharged to an inactive state in parallel with other circuit elements of the pre-charged address decode path.

Abstract: According to the present invention, a special operating mode of an integrated circuit device, such as a stress test mode, is entered while the integrated circuit device is powered up in order to avoid the large switching transients from multiple rows and columns being enabled simultaneously which would result if the stress test mode was entered after the integrated circuit device is powered up. Hence, power on reset can not be avoided by waiting until the power-on reset pulse is generated. The power on reset pulse of the integrated circuit device may be overridden or effectively disabled during a stress test mode, such that potential contention between the power-on reset pulse and the test mode signal of the integrated circuit device is eliminated. As a result, crowbar current is accordingly eliminated so that proper state initialization during a stress test mode may be accomplished.