Patents by Inventor Thomas Tetzlaff

Thomas Tetzlaff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230224724
    Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames through a Wireless Fidelity (Wi-Fi) Direct network such as a network of Peer-to-Peer (P2P) connections to extend the wireless range of the devices or access points beyond the transmission range of the individual devices or access points. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices, by allowing a station in the middle of two stations to serve as a relay station using the Wi-Fi Direct technology. Logic may enable relaying to avoid a full mesh technology such as is defined in IEEE 802.11s, since the full mesh technology may contain too many features that are not required for a simple or a static network configuration of such embodiments.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 13, 2023
    Applicant: Intel Corporation
    Inventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
  • Patent number: 11582617
    Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
  • Publication number: 20210334127
    Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
    Type: Application
    Filed: March 10, 2021
    Publication date: October 28, 2021
    Applicant: Intel Corporation
    Inventors: Yong JIANG, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
  • Patent number: 10949251
    Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Yong Jiang, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
  • Patent number: 10680749
    Abstract: A decoder having an input configured to receive a sequence of softbits presumed to correspond to a convolutionally-encoded codeword; and a decoding circuit configured to: determine, as part of a decoding process, a Maximum Likelihood (ML) survivor path in a trellis representation of the codeword; determine whether the presumed convolutionally-encoded codeword meets an early-termination criteria; and abort the decoding process if the presumed convolutionally-encoded codeword meets the early-termination criteria, continue the decoding process if the presumed convolutionally-encoded codeword fails to meet the early-termination criteria.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff
  • Patent number: 10349405
    Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAs) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
  • Publication number: 20190026149
    Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Inventors: Yong JIANG, Yuanyuan LI, Jianghong DU, Kuilin CHEN, Thomas A. TETZLAFF
  • Publication number: 20190007068
    Abstract: A decoder having an input configured to receive a sequence of softbits presumed to correspond to a convolutionally-encoded codeword; and a decoding circuit configured to: determine, as part of a decoding process, a Maximum Likelihood (ML) survivor path in a trellis representation of the codeword; determine whether the presumed convolutionally-encoded codeword meets an early-termination criteria; and abort the decoding process if the presumed convolutionally-encoded codeword meets the early-termination criteria, continue the decoding process if the presumed convolutionally-encoded codeword fails to meet the early-termination criteria.
    Type: Application
    Filed: July 1, 2017
    Publication date: January 3, 2019
    Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff
  • Publication number: 20180317224
    Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAs) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.
    Type: Application
    Filed: March 21, 2018
    Publication date: November 1, 2018
    Inventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
  • Patent number: 9980168
    Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
  • Publication number: 20180098229
    Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices.
    Type: Application
    Filed: August 7, 2017
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
  • Patent number: 9930661
    Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAB) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
  • Patent number: 9888407
    Abstract: Embodiments may implement a new hierarchical data structure for traffic indication mapping to facilitate transmissions for wireless communications devices. Many embodiments comprise MAC sublayer logic to generate and transmit management frames such as beacon frames with a partial virtual bitmap based upon the hierarchical data structure for traffic indication mapping. In some embodiments, the MAC sublayer logic may store the traffic indication map and/or the traffic indication map structure in memory, in logic, or in another manner that facilitates transmission of the frames. Some embodiments may receive, detect, and decode communications with frames comprising the partial virtual bitmap based upon the hierarchical data structure. In some embodiments, indications of buffered data for pages, blocks, sub-blocks, and/or stations may be inverted. In several embodiments, a new association identifier (AID) structure is defined for the new hierarchical data structure for traffic indication mapping.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Thomas J. Kenney, Emily H. Qi, Thomas A. Tetzlaff
  • Patent number: 9806921
    Abstract: A mobile communication device is provided that includes a receiver configured to receive a signal. The communication device further includes a calculation circuit configured to determine a cumulant value of an order higher than two of the received signal, to determine a function value of the determined cumulant value and to compare the determined function value with a predefined value. The communication device further includes a decoder configured to decode the received signal. The communication device further includes a target signal detector configured to activate the decoder based on the comparison of the function value with the predefined value.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: October 31, 2017
    Assignee: INTEL CORPORATION
    Inventors: David Arditti Ilitzky, Paulino Mendoza, Thomas Tetzlaff
  • Patent number: 9743399
    Abstract: Generally, embodiments to enable, indicate and detect Short Interframe Space (SIFS) of different time durations, a short (or small) SIFS which is shorter in duration than a regular SIFS, are described herein. Embodiments may comprise logic such as hardware and/or code to signal a short SIFS or a regular SIFS by setting or clearing a bit of a management frame transmitted by a station to an access point during the network association process, or by setting or clearing a bit in the SIG field of the preamble of a data unit transmitted by an access point to an associated station. In some embodiments, a third party station is able to receive the data unit sent by the access point, and decode, e.g., the SIG field bit to determine whether the short SIFS duration or regular SIFS duration is defined for the communication between the access point and the station.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Eldad Perahia, Thomas Tetzlaff, Thomas Kenney
  • Patent number: 9730082
    Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames through a Wireless Fidelity (Wi-Fi) Direct network such as a network of Peer-to-Peer (P2P) connections to extend the wireless range of the devices or access points beyond the transmission range of the individual devices or access points. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices, by allowing a station in the middle of two stations to serve as a relay station using the Wi-Fi Direct technology. Logic may enable relaying to avoid a full mesh technology such as is defined in IEEE 802.11s, since the full mesh technology may contain too many features that are not required for a simple or a static network configuration of such embodiments.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Emily H Qi, Adrian P Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
  • Patent number: 9730102
    Abstract: Logic may compress wireless communications frames and communicate compressed frames that do not include the duplicative bit sequences within the packet flow. Logic may include the compressed frames in flow frames. Logic may generate, encode, transmit, decode, parse, and interpret flow frames after a packet flow is created. Flow frames may comprise a flow frame control field, a compressed frame, and a frame sequence check. Logic may decompress the compressed flow frame based upon flow decompression rules associated with a flow index of the flow frame. Flow frames may include a duration field to set the network allocation vectors of other stations. And the frame sequence check may be generated based upon the entire flow frame.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventor: Thomas A. Tetzlaff
  • Publication number: 20170187554
    Abstract: A mobile communication device is provided that includes a receiver configured to receive a signal. The communication device further includes a calculation circuit configured to determine a cumulant value of an order higher than two of the received signal, to determine a function value of the determined cumulant value and to compare the determined function value with a predefined value. The communication device further includes a decoder configured to decode the received signal. The communication device further includes a target signal detector configured to activate the decoder based on the comparison of the function value with the predefined value.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: David Arditti llitzky, Paulino Mendoza, Thomas Tetzlaff
  • Patent number: 9559810
    Abstract: According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Thomas Tetzlaff, Minyoung Park
  • Publication number: 20160381643
    Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano