Abstract: Embodiments of the present invention may provide improved handling of communication characteristics, such as burstiness, latency-sensitive applications, bandwidth-sensitive applications, etc., to improve peak performance while not compromising other characteristics, such as thermal design power of the input/output chip packages. In an embodiment, in a control circuit that may be connected to and control a data transmitter, a method of transmitting data in a network may comprise receiving at least one feed-forward signal from the data transmitter, receiving at least one feedback signal from at least a first node of the network, comparing the at least one feed-forward signal with at least one threshold or condition, comparing the at least one feedback signal with at least one threshold or condition, and generating a signal indicating that a burst transmission should be started or stopped.

Abstract: Embodiments of the present invention may provide improved handling of communication characteristics, such as burstiness, latency-sensitive applications, bandwidth-sensitive applications, etc., to improve peak performance while not compromising other characteristics, such as thermal design power of the input/output chip packages. In an embodiment, in a control circuit that may be connected to and control a data transmitter, a method of transmitting data in a network may comprise receiving at least one feed-forward signal from the data transmitter, receiving at least one feedback signal from at least a first node of the network, comparing the at least one feed-forward signal with at least one threshold or condition, comparing the at least one feedback signal with at least one threshold or condition, and generating a signal indicating that a burst transmission should be started or stopped.

Abstract: A zero-crossing amplifier unit for use in high speed analog-digital-converters. A gain stage compares a sampling voltage at an input node with a provided threshold voltage to obtain a gain stage output signal. A voltage controlled current source provides a load current depending on a time window between an initial slope and an end slope of the gain stage output signal. A slope control means increases a duration of a rise and/or fall time of at least one of the initial and end slopes of the gain stage output signal.

Abstract: Embodiments are directed to feed-forward equalization. In some embodiments, a first circuit is configured to receive a signal transmitted over a channel as a differential pair, and a second circuit is configured to mirror the signal as at least a pre-cursor component comprising a first transistor of a first type of technology, a cursor component comprising a second transistor of a second type of technology, and a post-cursor component comprising a third transistor of the first type of technology.

Abstract: A zero-crossing amplifier unit for use in high speed analog-digital-converters. A gain stage compares a sampling voltage at an input node with a provided threshold voltage to obtain a gain stage output signal. A voltage controlled current source provides a load current depending on a time window between an initial slope and an end slope of the gain stage output signal. A slope control means increases a duration of a rise and/or fall time of at least one of the initial and end slopes of the gain stage output signal.

Abstract: Embodiments are directed to feed-forward equalization. In some embodiments, a first circuit is configured to receive a signal transmitted over a channel as a differential pair, and a second circuit is configured to mirror the signal as at least a pre-cursor component comprising a first transistor of a first type of technology, a cursor component comprising a second transistor of a second type of technology, and a post-cursor component comprising a third transistor of the first type of technology.

Abstract: A digital-to-analog (DAC) converter that includes a plurality of dynamically operated slave digital-to-analog (DAC) converters, each having a switched current mirror and a storage capacitor, and a static master digital-to-analog (DAC) converter in communication with the plurality of dynamically operated slave DAC converters, that distributes a current to at least one of the plurality of slave DAC converters such that voltage across the storage capacitor of the at least one slave DAC converter controls the switch current mirror so that the at least one slave DAC converter outputs currents that are equivalent to digital codes applied to the static master DAC converter. A ring counter is used to periodically refresh the charges on the storage capacitors that are lost by leakage. In addition to the periodic updates, an end user may perform immediate updates of selected slave DACs if necessary, via the ring counter.

Abstract: The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)?V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

Abstract: The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimized too. An example of an integrated line driver according to the invention comprises a first driver stage followed by a second driver stage, and a feedback unit forming with the second driver stage a control loop. The integrated line drivers are useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of ESD devices and process tolerances are minimized. Advantageously, the integrated line driver according to the invention complies with chip design methodologies, where 10 or more routing metal layers are used.

Abstract: The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)?V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).