Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.

Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.

Abstract: Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.

Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.

Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register.

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: A method for developing an integrated circuit chip design includes the steps of developing an architecture specification defining the functions of the chip, developing a microarchitecture specification based on the architecture specification, developing a functional and structural model of the chip based on the microarchitecture specification, designing software tools for use with the chip based on the architecture specification, and designing chip verification tools based on the microarchitecture specification. The activities associated with chip development are divided into phases which may be performed concurrently. The result of the development is an RTL model of the chip which can be utilized in implementation of products without comprising proprietary circuit, layout and fabrication process information of the entity that is implementing the products.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register. A user program could conceivably gain access to the supervisor mode by loading the target address of an event service routine, in the supervisor instruction address space, in the LOOP_BOT register and an address in the user instruction address space in the LOOP_TOP register. If the event occurred in the supervisor mode, the program flow could branch to the address in the LOOP_TOP register, giving the user program control in the supervisor mode. To avoid this potential security hazard, the processor may disable hardware loop operations when the processor exits the user mode.