Abstract: Strapping system to enable any ordinary backpack to become a drone carrier.

Abstract: A solar energy collecting module includes a frame that is assembled without using screws. The peripheral frame components are joined together using locking links and one or more ribs extend along the back side of the solar panel and are coupled to opposed sides of the frame. The ribs are coupled to the frames by an edge key fastener that includes opposed first flanges and opposed second flanges, the first flanges separated from the second flanges by a gap. The edge key fastener is inserted into an opening formed in a side wall of a frame component and rotated such that the opposed first flanges are disposed behind the side wall and within the frame and the opposed second flanges are received in a corresponding cavity formed in each of opposed ends of the rib.

Abstract: A frame member is disclosed for a mounting a solar panel in a solar module. Embodiments of the frame member include an elongated outer sleeve having a channel configured for receiving an elongated inner reinforcing member disposed therein. The reinforcing member may be slidably inserted into the channel in some embodiments and is operable to structurally strengthen the outer sleeve. The reinforcing member may be made of a material having a greater tensile strength than the outer sleeve. A method for assembling the frame is also provided.

Abstract: A solar energy collecting module includes a frame that is assembled without using screws. The peripheral frame components are joined together using locking links and one or more ribs extend along the back side of the solar panel and are coupled to opposed sides of the frame. The ribs are coupled to the frames by an edge key fastener that includes opposed first flanges and opposed second flanges, the first flanges separated from the second flanges by a gap. The edge key fastener is inserted into an opening formed in a side wall of a frame component and rotated such that the opposed first flanges are disposed behind the side wall and within the frame and the opposed second flanges are received in a corresponding cavity formed in each of opposed ends of the rib.

Abstract: A method and system for enhancing a materialized view. In one embodiment the method includes analyzing a defined query of the materialized view, checking the requirements of the materialized view log, generating execution scripts that automatically create and enhance the materialized view logs and tuning the materialized view.

Abstract: A suture clamping system, including a rod; and a clamp having a first end into which an end of the rod is received and a second end dimensioned to be snap-fit around the rod, the first and second ends being separated by a bendable mid-section. A method of clamping a suture, including positioning the suture between a clamp and a rod, wherein the clamp has a C-shaped cross section and is dimensioned to be snap-fit around the rod; and pushing the clamp against the rod such that the clamp snap-fits around the rod, thereby trapping the suture between the clamp and the rod.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A processing system including a vacuum chamber 24 and at least one tube 12 disposed through a wall 14 of the vacuum chamber 24 is described herein. A gas diffuser 22 is disposed in said tube 12, possibly at the end of the tube 12 and/or outside the chamber 24. The gas diffuser 22 is formed from a porous, possibly metallic, material which includes a plurality of microscopic holes whereby gas entering or leaving the vacuum chamber through the tube has a reduced force compared to if the gas diffuser 22 was not present. Other systems and methods are also disclosed.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: The surface of an integrated circuit, which uses reactive ion etching to pattern metal interconnection, is protected with two insulating layers on the surface. The first layer is a conventional silicon dioxide. The second layer is a photosensitive polymer which is the same as the material used for subsequent metalization of interconnection using the reactive ion etching technique. When the second layer is used, the reactive ion etching cannot attack the silicon dioxide.