Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract: A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

Abstract: In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which essentially covers the side walls of the lower source/drain region. A gate dielectric and a gate electrode, whose height is essentially equal to the height of the channel region, are formed on the side walls of the channel region.

Abstract: A first part (S/D1a) of a first source/drain region (S/D1) is disposed on at least one flank of a semiconductor structure (St) and on at least one peripheral region of a surface (OH), bordering the flank, of the semiconductor structure (St). A dimension of the first part (S/D1a) of the first source/drain region (S/D1) perpendicular to the flank is less than an analogous dimension of the semiconductor structure (St) and than the minimum feature size that can be made by the technology used. For the production, a mask that is used to create the semiconductor structure (St) can be reduced in size for the implantation of the first part (S/D1a) of the first source/drain region (S/D1). To make it easier to create a contact (K1) of the first source/drain region (S/D1), a second part (S/D1b) of the first source/drain region (S/D1) can be disposed in an inner region of the surface (OH) of the semiconductor structure (St).

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.

Abstract: The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite corners of the quadrilateral and outside the quadrilateral. Adjacent memory cells along a word line can be arranged in such a way that a first bit line and a second bit line of the adjacent memory cells coincide. The transistors are preferably vertical and are arranged at semiconductor structures (St1, St2, St3, St4, St5, St6) produced from a layer sequence. Two of the transistors having n-doped channel regions are preferably formed in each case on two semiconductor structures.

Abstract: Integrated circuit structure having an active microwave component and at least one passive component.A high-resistance silicon substrate (11) comprises an active microwave component (16) and at least two metallization planes (12, 14), which are insulated from one another by an insulation layer (13). A passive component surrounded by a grounded line (122) in one of the metallization planes (12) is provided, which comprises a first metal structure (121), which is realized in the first metallization plane (12), and a second metal structure (141), which is realized in the other metallization plane (14). The passive component is designed, in particular, as a capacitor, coil or resonator which comprises a capacitor and a coil.