Patents by Inventor Thomas V. Spencer
Thomas V. Spencer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923026Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: Seagate Technology LLCInventors: Jeremy B. Goolsby, Ryan J. Goss, Indrajit Prakash Zagade, Thomas V. Spencer, Jeffrey J. Pream, Christopher A. Smith, Charles McJilton
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Patent number: 11899952Abstract: A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.Type: GrantFiled: October 29, 2021Date of Patent: February 13, 2024Assignee: Seagate Technology LLCInventors: Ryan James Goss, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell
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Publication number: 20230305972Abstract: An apparatus may include a memory device, a memory controller, or both that can communicate via memory standard interfaces. However, the memory device may have physical memory that does not comply with the memory standard by itself. Disclosed herein are solutions that allow various non-standard types of memory, or emerging memory, to be utilized via a host, microprocessor, or memory controller that implements the interface standard. For example, by utilizing a command converter at the microprocessor and a tunneling register at the memory device, a microprocessor can send commands to the memory device by writing them to the tunneling register, which can then be processed at the memory device for operations to be performed with the non-standard or emerging memory.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Inventors: Jon D. Trantham, Steven Scott Williams, Paul M. Wiggins, Thomas V. Spencer
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Patent number: 11481342Abstract: A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.Type: GrantFiled: June 25, 2019Date of Patent: October 25, 2022Inventors: Robert Wayne Moss, Michael Shaw, Thomas V. Spencer, Yalan Liu, Sarvani Reddy Kolli
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Publication number: 20220137844Abstract: A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.Type: ApplicationFiled: October 29, 2021Publication date: May 5, 2022Inventors: Ryan J. Goss, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell
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Patent number: 11307768Abstract: A data storage system can employ namespace auto-routing by connecting a host to a data storage device via a system module. A data access request may be generated with the host and a namespace is then assigned to the data access request with a firmware upstream of the system module. An optimal physical data address in the data storage device can be assigned with the system module prior to writing the data associated with the data access request to the assigned physical data address of the assigned namespace.Type: GrantFiled: May 26, 2020Date of Patent: April 19, 2022Assignee: SEAGATE TECHNOLOGY LLCInventor: Thomas V. Spencer
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Publication number: 20220113898Abstract: A data storage system may have a plurality of memory cells located in different data storage devices that are arranged into a plurality of logical namespaces with each logical namespace configured to be sequentially written and entirely erased as a single unit. An asymmetry strategy may be proactively created with the asymmetry module in response to data access activity to the logical namespaces by the asymmetry module. A new mode, as prescribed by the asymmetry strategy, is entered for at least one logical namespace in response to an operational trigger being met. The new mode changes a timing of at least one queued data access request to at least one logical namespace.Type: ApplicationFiled: October 8, 2021Publication date: April 14, 2022Inventors: Stacey Secatch, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell, Steven Williams, Stephen H. Perlmutter
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Patent number: 11294572Abstract: A data storage system may have a number of data storage devices that each have a non-volatile memory connected to different first and second memory buffers. A data storage device can consist of a non-volatile memory where a data sector is stored. A network controller can consist of a buffer module connected to a first memory buffer and a second memory buffer that receives a data read request from the host for the data sector and evaluates the first and second memory buffers as a destination for the data sector after the data sector arrives at the buffer module. The buffer module may choose the first memory buffer and store the data sector in the first memory buffer prior to providing the data sector to the host to satisfy the data read request from the first memory buffer.Type: GrantFiled: July 6, 2017Date of Patent: April 5, 2022Assignee: Seagate Technology, LLCInventor: Thomas V. Spencer
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Publication number: 20220100407Abstract: A data storage system may have a data storage device with a memory arranged into a plurality of logical namespaces. A power module can be connected to the plurality of logical namespaces and configured to transition at least one memory cell in response to a workload computed for a namespace of the plurality of the logical namespaces to maintain a power consumption of 8 watts or less for the data storage device.Type: ApplicationFiled: September 30, 2021Publication date: March 31, 2022Inventors: Stacey Secatch, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lowell
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Publication number: 20220044754Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.Type: ApplicationFiled: August 5, 2021Publication date: February 10, 2022Inventors: Jeremy B. Goolsby, Ryan J. Goss, Indrajit Prakash Zagade, Thomas V. Spencer, Jeffrey J. Pream, Christopher A. Smith, Charles McJilton
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Patent number: 11157212Abstract: Method and apparatus for managing data transfers. In some embodiments, first and second storage devices respectively include first and second controllers, first and second local memories, and first and second non-volatile memories (NVMs). A virtual controller memory buffer (CMB) is formed from a dedicated portion of each of the first and second local memories for control by a host device. The first controller receives a virtual command set from the host device, and extracts a first local command to transfer data between the host device and the first NVM. In some cases, the second controller also receives the virtual command set and concurrently extracts a different, second local command to transfer data between the host device and the second NVM. Alternatively, the first controller may extract and forward the second local command to the second controller. The first and second NVMs may form an NVMe (Non-Volatile Memory Express) namespace.Type: GrantFiled: June 5, 2020Date of Patent: October 26, 2021Assignee: Seagate Technology, LLCInventors: Robert Wayne Moss, Thomas V. Spencer, Eric James Behnke
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Patent number: 11113002Abstract: A data storage device includes a controller configured to recognize commands received from a host as single logical address (LA) commands or multi-LA commands. The data storage drive also includes a command overlap detection table having a plurality of records with each record configured to store multiple unrelated LAs associated with different single LA commands and configured to store multiple related LAs associated with a single multi-LA command.Type: GrantFiled: October 25, 2019Date of Patent: September 7, 2021Assignee: Seagate Technology LLCInventor: Thomas V. Spencer
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Publication number: 20210191657Abstract: Method and apparatus for managing data transfers. In some embodiments, first and second storage devices respectively include first and second controllers, first and second local memories, and first and second non-volatile memories (NVMs). A virtual controller memory buffer (CMB) is formed from a dedicated portion of each of the first and second local memories for control by a host device. The first controller receives a virtual command set from the host device, and extracts a first local command to transfer data between the host device and the first NVM. In some cases, the second controller also receives the virtual command set and concurrently extracts a different, second local command to transfer data between the host device and the second NVM. Alternatively, the first controller may extract and forward the second local command to the second controller. The first and second NVMs may form an NVMe (Non-Volatile Memory Express) namespace.Type: ApplicationFiled: June 5, 2020Publication date: June 24, 2021Inventors: Robert Wayne Moss, Thomas V. Spencer, Eric James Behnke
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Publication number: 20210124525Abstract: A data storage device includes a controller configured to recognize commands received from a host as single logical address (LA) commands or multi-LA commands. The data storage drive also includes a command overlap detection table having a plurality of records with each record configured to store multiple unrelated LAs associated with different single LA commands and configured to store multiple related LAs associated with a single multi-LA command.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Inventor: Thomas V. Spencer
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Publication number: 20200409874Abstract: A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Robert Wayne Moss, Michael Shaw, Thomas V. Spencer, Yalan Liu, Sarvani Reddy Kolli
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Publication number: 20200387307Abstract: A data storage system can employ namespace auto-routing by connecting a host to a data storage device via a system module. A data access request may be generated with the host and a namespace is then assigned to the data access request with a firmware upstream of the system module. An optimal physical data address in the data storage device can be assigned with the system module prior to writing the data associated with the data access request to the assigned physical data address of the assigned namespace.Type: ApplicationFiled: May 26, 2020Publication date: December 10, 2020Inventor: Thomas V. Spencer
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Patent number: 10613985Abstract: Method and apparatus for managing data buffers in a data storage device. In some embodiments, a write manager circuit stores user data blocks in a write cache pending transfer to a non-volatile memory (NVM). The write manager circuit sets a write cache bit value in a forward map describing the NVM to a first value upon storage of the user data blocks in the write cache, and subsequently sets the write cache bit value to a second value upon transfer of the user data blocks to the NVM. A read manager circuit accesses the write cache bit value in response to a read command for the user data blocks. The read manager circuit searches the write cache for the user data blocks responsive to the first value, and retrieves the requested user data blocks from the NVM without searching the write cache responsive to the second value.Type: GrantFiled: July 6, 2017Date of Patent: April 7, 2020Assignee: Seagate Technology LLCInventors: Thomas V. Spencer, Matthew Lovell
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Patent number: 10564890Abstract: A data storage system may have a number of data storage devices that each have a non-volatile memory connected to a memory buffer. The memory buffer can consist of a map unit having a predetermined size. In receipt of a data sector into the map unit of the memory buffer, the data sector may be identified as a runt with a runt module connected to the memory buffer and the non-volatile memory. The runt module can generate and subsequently execute a runt handling plan to fill the size of the map unit before storing the filled map unit in the non-volatile memory.Type: GrantFiled: July 7, 2017Date of Patent: February 18, 2020Assignee: Seagate Technology LLCInventors: Matthew Lovell, Thomas V. Spencer, Ryan James Goss
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Patent number: 10248357Abstract: A data storage system may have a first data storage device and a second data storage device connected with a host via a network. The network can consist of a network controller having a message module that generates a buffer progression plan and then assigns a first system message to a first buffer and first computing unit of the first data storage device and assigns a second system message to a second buffer and second computing unit of the second data storage device. The respective first and second computing units may then service the first and second system messages.Type: GrantFiled: July 6, 2017Date of Patent: April 2, 2019Assignee: Seagate Technology LLCInventor: Thomas V. Spencer
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Publication number: 20190013086Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner