Patents by Inventor Thomas Vogelsang
Thomas Vogelsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153548Abstract: Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.Type: ApplicationFiled: November 6, 2023Publication date: May 9, 2024Inventors: Frederick A. Ware, Thomas Vogelsang, Michael Raymond Miller, Collins Williams
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Publication number: 20240146336Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Inventors: Thomas Vogelsang, Michael Alexander Hamburg, John Eric Linstadt, Evan Lawrence Erickson
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Publication number: 20240146546Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fingerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.Type: ApplicationFiled: February 25, 2022Publication date: May 2, 2024Inventors: Scott C. BEST, Thomas VOGELSANG, Michael Alexander HAMBURG, Mark Evan MARSON, Helena HANDSCHUH, HAMPEL E. Craig, Kenneth Lee WRIGHT
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Patent number: 11972121Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.Type: GrantFiled: February 25, 2021Date of Patent: April 30, 2024Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Liji Gopalakrishnan
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Publication number: 20240127882Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.Type: ApplicationFiled: October 30, 2023Publication date: April 18, 2024Inventors: Thomas VOGELSANG, John Eric Linstadt, Liji Gopalakrishnan
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Publication number: 20240127903Abstract: A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.Type: ApplicationFiled: September 26, 2023Publication date: April 18, 2024Inventors: Thomas Vogelsang, Torsten Partsch
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Publication number: 20240119995Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.Type: ApplicationFiled: October 18, 2023Publication date: April 11, 2024Inventor: Thomas VOGELSANG
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Publication number: 20240118837Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.Type: ApplicationFiled: October 16, 2023Publication date: April 11, 2024Inventors: Frederick A. Ware, Thomas Vogelsang
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Patent number: 11934654Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.Type: GrantFiled: December 7, 2021Date of Patent: March 19, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang
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Publication number: 20240086112Abstract: A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.Type: ApplicationFiled: September 19, 2023Publication date: March 14, 2024Inventor: Thomas Vogelsang
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Patent number: 11922066Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.Type: GrantFiled: January 14, 2022Date of Patent: March 5, 2024Assignee: Rambus Inc.Inventors: Thomas Vogelsang, Michael Raymond Miller, Steven C. Woo
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Publication number: 20240062788Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.Type: ApplicationFiled: September 26, 2023Publication date: February 22, 2024Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
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Patent number: 11908515Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.Type: GrantFiled: January 18, 2023Date of Patent: February 20, 2024Assignee: Hefei Reliance Memory LimitedInventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
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Patent number: 11894093Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.Type: GrantFiled: January 4, 2022Date of Patent: February 6, 2024Assignee: Rambus Inc.Inventor: Thomas Vogelsang
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Patent number: 11868619Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.Type: GrantFiled: December 3, 2020Date of Patent: January 9, 2024Assignee: Rambus Inc.Inventors: Liji Gopalakrishnan, Thomas Vogelsang, John Eric Linstadt
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Patent number: 11842761Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.Type: GrantFiled: July 30, 2021Date of Patent: December 12, 2023Assignee: Rambus Inc.Inventors: Thomas Vogelsang, John Eric Linstadt, Liji Gopalakrishnan
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Patent number: 11842762Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.Type: GrantFiled: March 16, 2020Date of Patent: December 12, 2023Assignee: Rambus Inc.Inventors: Frederick Ware, Thomas Vogelsang, Michael Raymond Miller, Collins Williams
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Publication number: 20230395118Abstract: A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.Type: ApplicationFiled: June 6, 2023Publication date: December 7, 2023Inventors: Thomas VOGELSANG, Torsten PARTSCH
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Publication number: 20230377668Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.Type: ApplicationFiled: April 24, 2023Publication date: November 23, 2023Inventors: Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
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Patent number: 11823734Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.Type: GrantFiled: November 26, 2019Date of Patent: November 21, 2023Assignee: Rambus Inc.Inventor: Thomas Vogelsang