Abstract: A semiconductor device is described in which an integrated circuit executes dummy operating cycles in order to generate heat if the temperature of the semiconductor device drops below a lower limit value. In this manner the semiconductor device can be rated for lower temperatures than the construction tolerances of the semiconductor device would allow.

Abstract: A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Abstract: A semiconductor device is described in which an integrated circuit executes dummy operating cycles in order to generate heat if the temperature of the semiconductor device drops below a lower limit value. In this manner the semiconductor device can be rated for lower temperatures than the construction tolerances of the semiconductor device would allow.

Abstract: A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Abstract: An apparatus for function testing of electronic circuits includes a tester array having a terminal. A test circuit has at least two resistor elements, a common circuit node connected to the resistor elements for connection to the terminal of the tester array, and terminals of the resistor elements each being remote from the circuit node for connection to a respective output of an electronic circuit to be tested. A testing method for function testing of electronic circuits with such an apparatus includes placing the electronic circuit into a state in which signals are present at an output of the electronic circuit to be tested. The electronic circuit is function tested with respect to a resultant signal being established at the common circuit node.

Abstract: A board includes a plurality of integrated circuits operating at a first supply potential to be supplied. The board has a potential adaptation configuration with an output potential being the first supply potential and an input potential being a second supply potential to be supplied to the board.

Abstract: In an integrated semiconductor memory circuit and a method for its operation, the circuit includes devices by means of which second electrodes of memory capacitors of dummy memory cells are acted upon by a precharging potential. The precharging potential has a value being 5 to 35% greater than a value of half a difference between a supply voltage potential and a reference potential.

Abstract: An integrated semiconductor memory circuit includes devices through which second electrodes of memory capacitors of dummy memory cells are to be acted upon with a precharging potential. The precharging potential has a value being 5 to 35% greater than a value of a bit line potential to which bit lines of the semiconductor memory circuit are to be precharged. A method for operating an integrated semiconductor memory circuit includes precharging the bit lines to the bit line potential, prior to a readout of data stored in memory cells, and applying the precharging potential to the second electrodes of the memory capacitors of the dummy memory cells, in the precharging of the bit lines.