Abstract: Some embodiments include apparatus, systems, and methods having storage units coupled in parallel between a first line and a second line and a comparator circuit coupled to the second line. The first line may be configured to provide different voltages. The comparator circuit may be configured to compare a first current on the second line with a second current to provide an output signal.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array.