Abstract: Aspects of the present disclosure involve systems, methods, and the like, for an electrochemical sensing platform for point-of-care diagnostic applications. The ES platform may include functionality for many types of ES applications, including but not limited to, voltammetry, galvanometry, amperometry, and electrochemical impedance spectroscopy (EIS). In some embodiments, the platform includes sensor analog front end, stimulus generation, analog sensor data acquisition and conditioning, digital-to-analog conversion, back-end digital signal processing, wired or wireless interface, and a user application for interacting with the platform. In some embodiments, the platform includes a number of functional modules to provide a low cost and high mobility to the device, while maintaining the performance specifications. Signal generation, digital data acquisition/processing may be managed by an on-board microcontroller or off-board computing device.

Abstract: An Ussing chamber assembly for assessing a tissue sample and for receiving a first fluid and a second fluid during such assessment is disclosed. The Ussing chamber assembly includes an Ussing chamber configured to be separated by the tissue sample into a first chamber portion and a second chamber portion. The assembly includes a first channel in fluidic communication with the first chamber portion, a second channel in fluidic communication with the second chamber portion, and at least three electrical conductors in fluidic communication with the first chamber portion.

Abstract: A well plate for measuring an analyte in a sample is disclosed. The well plate includes at least a first, a second, and a third electrode. The first electrode has a higher sensitivity to a first analyte than the second and third electrodes. The second electrode has a higher sensitivity to a second analyte than the first and third electrodes.

Abstract: Aspects of the present disclosure involve systems, methods, and the like, for an electrochemical sensing platform for point-of-care diagnostic applications. The ES platform may include functionality for many types of ES applications, including but not limited to, voltammetry, galvanometry, amperometry, and electrochemical impedance spectroscopy (EIS). In some embodiments, the platform includes sensor analog front end, stimulus generation, analog sensor data acquisition and conditioning, digital-to-analog conversion, back-end digital signal processing, wired or wireless interface, and a user application for interacting with the platform. In some embodiments, the platform includes a number of functional modules to provide a low cost and high mobility to the device, while maintaining the performance specifications. Signal generation, digital data acquisition/processing may be managed by an on-board microcontroller or off-board computing device.

Abstract: A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.

Abstract: A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples.

Abstract: A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method.

Abstract: A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.

Abstract: A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method.

Abstract: A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples.

Abstract: Systems and methods associated with costs of a selected objective are disclosed. One embodiment of a system may comprise a constraint evaluator that evaluates a value set associated with a plurality of objectives to determine if a non-selected objective has violated at least one constraint. The system may further comprise a cost function configurable to evaluate a cost associated with the value set at a first cost range if the value set violates the at least one constraint associated with the non-selected objective, and to evaluate a cost associated with the value set at a second cost range associated with the selected objective if the value set does not violate the at least one constraint associated with the non-selected objective, such that the second cost range is different from the first cost range.

Abstract: Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations associated with dynamic and static power related parameters of a circuit design. The power characterizations can be determined prior to circuit design optimizations, stored and utilized during circuit design optimizations.

Abstract: A method for analyzing coupling between interconnects in a VLSI processor to simulate the impact of process variations by the use of model-fitted equations to determine a delay change curve for a coupled interconnect. Simulated curves are first used to determine the parameters in the model-fitted equations. These model-fitted equations are then used to derive the output waveform at the output of a victim line using superposition of noise waveforms calculated for a plurality of aggressors. The output waveform is then quadratically expanded to obtain the delay change curve, and the statistical mean and the standard deviation of the victim delay through the coupled interconnect are calculated by using said quadratic function and the statistical behavior of all inputs to the coupled interconnect.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: An indication of power associated with one or more power consuming units of is determined based on simulation data. The simulation data can be generated over a plurality of testcases. A Bayesian-based statistical model utilizes the simulation data to estimate a parameter indicative of power associated with the one or more power consuming units. A corresponding indication of power is computed based on the estimated parameter.

Abstract: An indication of power for one or more units of a circuit design are determined based on functional verification data. The functional verification data can be generated for input vectors applied to a representation of the circuit design to functionally verify operation of the design.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: A method of optimizing speed and power consumption of an integrated circuit having at least one path having at least one gate involves creating a parent state representing a partition of the integrated circuit design. Each device in the parent state further has associated device size information and device type information. A population of individual states are created from at least one parent states. These individual states are scored for timing and power dissipation. Survivor individual states of the population are determined based upon scores of each state of the population. The steps of creating the population of individual states, scoring states, and determining survivor states, are iterated as needed. Survivor states are then further optimized with a greedy search, and a best individual survivor state is selected as an optimized state of each partition. The integrated circuit netlist is adjusted to correspond to the optimized state.

Abstract: A method of calculating a crossover current component of dynamic power dissipation at a gate of a CMOS integrated circuit design is operable on a digital computer. The method includes deriving two constants. An effective width is computed for the gate, a transition time is computed at an input of the gate, an activity ratio is determined for the gate, and a load capacitance is computed at an output of the gate. The effective width is multiplied by the activity ratio, the clock rate, and the difference of the first constant multiplied by the transition time and the second constant multiplied by the load capacitance to determine a crossover current component of dynamic power of the gate.