Patents by Inventor Thomas W. Jetton

Thomas W. Jetton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clearance size reduction for backdrilled differential vias
    Patent number: 10863628
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 8, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • CLEARANCE SIZE REDUCTION FOR BACKDRILLED DIFFERENTIAL VIAS
    Publication number: 20200053880
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Matthew TWAROG, Hui HE, Thomas W. JETTON
  • Clearance size reduction for backdrilled differential vias
    Patent number: 10470311
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • CLEARANCE SIZE REDUCTION FOR BACKDRILLED DIFFERENTIAL VIAS
    Publication number: 20190098765
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Matthew TWAROG, Hui He, Thomas W. Jetton
  • Heat sink with mounted power supply
    Patent number: 9867317
    Abstract: An apparatus may include a heat sink to be mounted to a printed circuit board. The apparatus may include a power supply mounted to the heat sink. The power supply may receive input power and supply output power to one or more components of the printed circuit board.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 9, 2018
    Assignee: Juniper Networks, Inc.
    Inventor: Thomas W. Jetton