Patents by Inventor Thomas W. Keller

Thomas W. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7340378
    Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Soraya Ghiasi, Thomas W. Keller, Jr., Karthick Rajamani, Freeman Leigh Rawson, III, Juan C. Rubio
  • Patent number: 6985952
    Abstract: Cluster systems having central processor units (CPUs) with multiple processors (MPs) are configured as high density servers. Power density is managed within the cluster systems by assigning a utilization to persistent states and connections within the cluster systems. If a request to reduce overall power consumption within the cluster system is received, persistent states and connections are moved (migrated) within the multiple processors based on their utilization to balance power dissipation within the cluster systems. If persistent connections and states, that must be maintained have a low rate of reference, they may be maintained in processors that are set to a standby mode where memory states are maintained. In this way the requirement to maintain persistent connections and states does not interfere with an overall strategy of managing power within the cluster systems.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Thomas W. Keller, Michael D. Kistler, Freeman L. Rawson, III
  • Publication number: 20030084154
    Abstract: Cluster systems having central processor units (CPUs) with multiple processors (MPs) are configured as high density servers. Power density is managed within the cluster systems by assigning a utilization to persistent states and connections within the cluster systems. If a request to reduce overall power consumption within the cluster system is received, persistent states and connections are moved (migrated) within the multiple processors based on their utilization to balance power dissipation within the cluster systems. If persistent connections and states, that must be maintained have a low rate of reference, they may be maintained in processors that are set to a standby mode where memory states are maintained. In this way the requirement to maintain persistent connections and states does not interfere with an overall strategy of managing power within the cluster systems.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Thomas W. Keller, Michael D. Kistler, Freeman L. Rawson
  • Patent number: 5355487
    Abstract: The invention disclosed herein is a system and method for comprehensive, non-invasive profiling of a processor whereby feedback is provided to a programmer of the execution dynamics of a program. In a preferred embodiment a partial real-time reduction is provided of selected trace events employing the environment's trace facility, and a post-processing function is then performed. A trace hook is provided in the environment's periodic clock routine which captures the address to be returned to following this timer's interrupt, and further captures the address of the caller of the routine represented by the first address. The frequency of occurrences of the first address is collected and correlated to various virtual address spaces and corresponding subroutine offsets within those virtual address spaces.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: October 11, 1994
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Keller, Robert J. Urquhart