Abstract: A linear and symmetrical gigaohm resistive load structure for an integrated circuit is implemented using a thin film accumulation mode MOSFET configured as a split gate symmetrically off device. Preferably, the resistive load structure comprises two thin film accumulation mode field effect transistors connected in series with a common node and separate gate electrodes. The thin film devices are provided with undoped or lightly doped polysilicon channel regions to provide a desired gigaohm resistance value. By connecting each of the two gate electrodes to the respective source terminals, a two terminal gigaohm resistor structure is produced in which one of the devices is always in the high impedance OFF state regardless of the terminal voltages. The split gate structure allows the integration of the device with minimal metallization interconnect and only two terminals.

Abstract: A silicon-on-insulator substrate having a very low threading dislocation density is made by implanting oxygen ions into a silicon substrate while heating the substrate to form a layer of silicon dioxide buried in the silicon substrate and annealing the implanted substrate at high temperature in a novel furnace incorporating a polysilicon tube to constrain the annealing temperature to be uniform over the entire substrate. The silicon-on-insulator substrate is particularly useful for the manufacture of semiconductor devices formed in thin silicon films.

Abstract: A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.

Abstract: In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.