Abstract: Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.

Abstract: A CAN node having an enhanced fault recovery system is disclosed. The CAN node includes a CAN protocol controller device which reconnects to a CAN bus from the node's busoff state only after the node has successfully decoded 128 good messages from other devices on the CAN bus. Such a system advantageously provides a CAN node which exits its busoff state with a high degree of confidence that the fault that caused the node to enter the busoff state has been cleared. The protocol controller device uses the eleven recessive bits that start at the acknowledgement delimiter and finish at the end of the third bit of intermission to recognize that a single message has been successfully decoded.

Abstract: A method for summing a sequence of binary product terms utilizing a modified Booth's algorithm in an arithmetic unit, wherein the arithmetic unit has a multiplicand register, a multiplier register, a data bus coupled to the multiplicand register and to the multiplier register, a pad bit located adjacent to the least signficant bit of the multiplier register, and an adder register coupled to the multiplicand register. After initializing the adder register, the values of the pad bit and the two least significant bits of the multiplier register are examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the examined values. The multiplier value is then shifted 2 places to the right, through the pad bit, and the multiplicand value is shifted 2 places to the left.

Abstract: An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow.

Abstract: An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.

Abstract: An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms.