Abstract: A method for evaluating indicators of compromise (IOCs) is performed at a device having one or more processors and memory. The method includes receiving respective specifications of a plurality of IOCs, wherein the respective specifications of each IOC of the plurality of IOCs includes a respective cost associated with evaluating the IOC. The method further includes dynamically determining an order for evaluating the plurality of IOCs based on the respective costs associated with the plurality of IOCs, and determining whether a threat is present based on results for evaluating one or more of the plurality of IOCs in accordance with the dynamically determined order, instead of an order by which the plurality of IOCs have been received at the device.

Abstract: A method for evaluating indicators of compromise (IOCs) is performed at a device having one or more processors and memory. The method includes receiving respective specifications of a plurality of IOCs, wherein the respective specifications of each IOC of the plurality of IOCs includes a respective cost associated with evaluating the IOC. The method further includes dynamically determining an order for evaluating the plurality of IOCs based on the respective costs associated with the plurality of IOCs, and determining whether a threat is present based on results for evaluating one or more of the plurality of IOCs in accordance with the dynamically determined order, instead of an order by which the plurality of IOCs have been received at the device.

Abstract: Embodiments of the present invention provide a system, method, and program product for transferring an executing application to a second computer. A first computer includes an executing application, wherein the first computer executes a first cross-platform hypervisor, and wherein the application includes a graphical state and a memory state. The first computing receives a signal to transfer the executing application to the second computer, which is executes a second cross-platform hypervisor, and halts the executing application. The first computer transfers the graphical state and the memory state of the executing application to the second computer, utilizing any suitable protocol capable of transferring the graphical state and the memory of the executing application from the first computer to the second computer, wherein execution of the executing application resumes on the second computer.

Abstract: An automatic addressing technique for flexibly specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern.

Abstract: A boundary scan bus error reporting circuitry loads an unused sentinel bit pattern into the boundary scan instruction register in a conventional error reporting boundary scan test system. The unused sentinel bit pattern signifies that a fault exists somewhere upstream of the instruction register in the boundary scan circuitry associated with a specific integrated circuit. The special sentinel pattern is loaded into the instruction register in response to an illegal instruction control signal generated by an instruction decoder coupled to the instruction latch in the boundary scan architecture.