Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A method for testing bipolar transistors in an integrated circuit includes first measuring first conductances of leakage paths between collectors and emitters of a first plurality of bipolar transistors with a known number of defects, calculating a per defect conductance value using the measured first conductances and the known number of defects to derive the linear relation. The method then measures second conductances of leakage path between collectors and emitters of a second plurality of bipolar transistors under test and having an unknown number of defects. Using the measured leakage path current from the second conductances and the linear relation, the number of defects related to the second plurality of bipolar transistors under test may be accurately determined.

Abstract: A system for reducing the concentration of foreign material on a wafer etched in a reactive ion etch chamber is disclosed. As a radio frequency voltage is applied within the etch chamber, the pressure within the etch chamber may be reduced to a base pressure. Also, the flow of gas into the etch chamber may be maintained. This may include minimizing the flow of high reactive gas into the etch chamber while maintaining the flow of low reactive gas therein. The system further includes deactivating the radio frequency voltage. Deactivating the radio frequency voltage may be accomplished by gradually reducing the voltage to a minimum voltage. The gradual reduction may be accomplished by incrementally reducing the voltage in a series of steps. If reactive ion etching occurs with magnetic enhancements, the magnetic field applied to the etch chamber may be deactivated, typically prior to the reduction of the radio frequency voltage.