Patents by Inventor Thomas W. Winter

Thomas W. Winter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
    Patent number: 7960840
    Abstract: A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Thomas W. Winter, William R. Morrison, Gregory D. Winterton, Asad M. Haider
  • DOUBLE WAFER CARRIER PROCESS FOR CREATING INTEGRATED CIRCUIT DIE WITH THROUGH-SILICON VIAS AND MICRO-ELECTRO-MECHANICAL SYSTEMS PROTECTED BY A HERMETIC CAVITY CREATED AT THE WAFER LEVEL
    Publication number: 20090280602
    Abstract: A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
    Type: Application
    Filed: May 11, 2009
    Publication date: November 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer BONIFIELD, Thomas W. WINTER, William R. MORRISON, Gregory D. WINTERTON, Asad M. HAIDER
  • Method and apparatus for predicting device yield from a semiconductor wafer
    Patent number: 6707936
    Abstract: Device design information (18) for a semiconductor device is used to generate theoretical probability of failure information (21), which represents the probability that a manufacturing defect will cause an electrical failure in an actual device fabricated according to the design information. An actual wafer (23), which contains a plurality of devices (22) manufactured according to the design information, is inspected for actual defects (25). The probability of failure information is then used to determine for each of several detected defects a corresponding probability value. Then, the individual probability values for the respective defects are combined in order to obtain a composite failure probability, which serves as a basis for evaluating the expected yield of operational devices from the particular wafer.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas W. Winter, Thomas K. Powell, Jr., Steven M. James