Patents by Inventor Thomas Waas

Thomas Waas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout
    Patent number: 6892367
    Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 10, 2005
    Assignee: PDF Solutions, Inc.
    Inventors: Michal Palusinski, Mariusz Niewczas, Wojciech Maly, Andrezej Strojwas, Thomas Waas, Hans Eisenmann
  • Method of correcting physically-conditioned errors in measurement of microscopic objects
    Patent number: 6795574
    Abstract: A method of correcting physically conditioned errors in the measurement of an object detects an image of the object to be measured, measures the imaged object, determines a measurement error caused by structural surroundings of the object, and corrects the measurement result in dependence on the measurement error.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: September 21, 2004
    Assignee: Applied Integrated Systems & Software
    Inventors: Hans Hartmann, Thomas Waas, Hans Eisenmann, Hans-Juergen Brueck
  • Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout
    Publication number: 20040003357
    Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Michal Palusinski, Mariusz Niewczas, Wojciech Maly, Andrezej Stojwas, Thomas Waas, Hans Eisenmann
  • Procedure for generating information for producing a pattern defined by design information
    Patent number: 6107207
    Abstract: A method for generating information for producing a pattern, defined by design information on a medium, using at least one direct-writing pattern generating process, which first provides the design information and then calculates correction data based on the provided design information and depending on the pattern generating process which corrects pattern faults in the pattern to be generated which were caused by the pattern generating process. The design and correction information is then separately provided to the direct-writing pattern generating process for its activation.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: August 22, 2000
    Assignee: Applied Integrated Systems & Software
    Inventors: Thomas Waas, Hans Hartmann