Patents by Inventor Thomas Waayers

Thomas Waayers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070208970
    Abstract: According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.
    Type: Application
    Filed: January 13, 2005
    Publication date: September 6, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONCIS N.V.
    Inventors: Erik Marinissen, Thomas Waayers
  • Publication number: 20060100810
    Abstract: An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells (14) transport data serially along the boundary scan chain while selectable second ones of the cells (14) write or read data that has been or will be transported through the first ones of the cells (14) in the further mode to or from the terminals (16) from or to the scan chain.
    Type: Application
    Filed: January 28, 2004
    Publication date: May 11, 2006
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Leon Maria Van De Logt, Thomas Waayers, Frank Van Der Heyden
  • Publication number: 20050268193
    Abstract: A module (100) has test controller (140) for evaluating a functional block (120). The test controller (140) includes a first register (142) coupled between an input pin (162) and an output pin (164) from a plurality of pins (160) and a second register (144) coupled to the first register (142) for capturing an update of the content of the first register (142) responsive to an update signal from a decoder (170). The second register (144) is further arranged to generate evaluation control signals (145). The test controller further includes dedicated control circuitry including a plurality of logic gates (180) and a first logic gate (182). The plurality of logic gates is arranged to decode the content of the first register (142) and provide the first logic gate (182) with a resulting gating signal for blocking the update of the second register (144). Consequently, the dedicated control circuitry is able to prevent undesired changes in the module (100) during an evaluation mode of for instance another module.
    Type: Application
    Filed: July 17, 2003
    Publication date: December 1, 2005
    Applicant: Koninklijke Philips Electronics N.V.
    Inventor: Thomas Waayers