Patents by Inventor Thomas Warren Savage

Thomas Warren Savage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230153422
    Abstract: A computer-implemented method, and system, for detecting modification of a semiconductor device includes generating and applying an exhaustive first set of patterns to a netlist golden model of a golden device. The exhaustive first set of patterns is developed by a pseudorandom number generator. Applying the patterns to stimulate the device produces a first response serial bit stream in relation to logical composition of the golden model. A signature analyzer compresses the total output to provide a first cyclic redundancy code or answer. The same exhaustive set of patterns can be provided to stimulate the model of an unknown device. The unknown device is shown to be identical to the golden device if its answer matches that of the golden device and modified if its answer does not match that of the golden device.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Applicant: Rocksavage Technology, Inc.
    Inventor: Thomas Warren Savage
  • Patent number: 10296491
    Abstract: Embodiments disclosed include computer implemented systems and methods comprising multiple computer programs that when used together as part of the system enable the detection of one set of computer files within another set of files without having direct access to the files themselves. A computer program generated unique fingerprint for each set of files that is a condensed representation of that file that ensures no reverse engineering is possible from its use. Another computer program serves as a public repository to securely store fingerprints from multiple sources (e.g. companies).Additionally, another computer program is used to analyze the two or more file sets and produces a report that shows whether files in one set are contained in the other.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: May 21, 2019
    Assignee: Silvaco, Inc.
    Inventors: Thomas Warren Savage, Michael Cizl, Jeffrey Allen Roberts
  • Publication number: 20170103079
    Abstract: Embodiments disclosed include computer implemented systems and methods comprising multiple computer programs that when used together as part of the system enable the detection of one set of computer files within another set of files without having direct access to the files themselves. A computer program generated unique fingerprint for each set of files that is a condensed representation of that file that ensures no reverse engineering is possible from its use. Another computer program serves as a public repository to securely store fingerprints from multiple sources (e.g. companies).Additionally, another computer program is used to analyze the two or more file sets and produces a report that shows whether files in one set are contained in the other.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Inventors: Thomas Warren Savage, Michael Cizl, Jeffrey Allen Roberts
  • Patent number: 6601024
    Abstract: An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: July 29, 2003
    Assignee: Synopsys, Inc.
    Inventors: Shivakumar Shankar Chonnad, Thomas Warren Savage, Manickam E. Kandaswamy, Maulin Bhatt, Christopher A. Kopetzky
  • Patent number: RE37613
    Abstract: An automatic addressing technique for flexibility specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: March 26, 2002
    Assignee: Compaq Cupertino Corporation
    Inventor: Thomas Warren Savage