Abstract: Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Abstract: A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

Abstract: A communication system and method with configurable posting points have been described.

Abstract: A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain, the first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with the Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than the write side clock, comprising: a register file; a first interface to the first finite state machine; a second interface to the second finite state machine; and logic for loading in accordance with the write side clock, a communication queue of the information into the register file in accordance with the Request signals from the first finite state machine, for reading by the second finite state machine via the second interface in accordance with the read side clock.