Abstract: A photoresin formulation for volumetric additive manufacturing contains a photo-curable mixture of: a monomer (e.g., an acrylate-based monomer); a photoinitiator; a polymerization inhibitor (e.g., molecular oxygen (O2)); and, a reducing agent reactive with a free radical species (e.g., a peroxyl radical) formed from the polymerization inhibitor. The reducing agent permits faster printing of objects from the photoresin formulation in a volumetric additive manufacturing process to produce 3D objects of high fidelity.

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 1 wt % to about 12 wt % of BVE; and c. from about 1 wt % to about 12 wt % of at least two fatty alcohols.

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 0.25 wt % to about 8 wt % of BVE; and c. from about 0.25 wt % to about 8 wt % of fatty alcohol(s).

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 1 wt % to about 12 wt % of BVE; and c. from about 1 wt % to about 12 wt % of at least two fatty alcohols.

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 0.25 wt % to about 8 wt % of BVE; and c. from about 0.25 wt % to about 8 wt % of fatty alcohol(s).

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 1 wt % to about 12 wt % of BVE; and c. from about 1 wt % to about 12 wt % of at least two fatty alcohols.

Abstract: A hair conditioner composition comprising: a. an aqueous carrier; b. from about 1 wt % to about 12 wt % of BVE; and c. from about 1 wt % to about 12 wt % of at least two fatty alcohols.

Abstract: The invention is directed to an educational system for use in instruction of educational concepts while playing a game. The system consists of a game sheet having an illustration for use in instruction of an educational concept, a set of magnetic playing pieces associated with the game sheet, and a display unit for receiving the game sheet and the magnetic playing pieces. The display unit has first and second display sides, each of which have a magnetized panel for attracting magnetic playing pieces. Further, a frame member adjacent the panel covers at least a portion of the panel, and has a game sheet receiving slot in the frame member is used for inserting and removing the game sheet.

Abstract: The invention concerns a method which consists in using a single-piece casing (1), without break; then for a first cleaning process, in cutting the casing (1) between the zone (4) containing the filter and the zone (6) containing the other element; then in cleaning the part containing the particle filter; and in assembling once more the two parts, so that the global dimensions of the casing (1) are substantially unchanged.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory installed in the computer system is determined. A minimum number of sub-blocks for the cache memory is selected such that when less than the maximum amount of system memory is installed, fewer sub-blocks are selected for each block in the cache memory. Based on the optimal number of sub-blocks selected for the amount of installed memory, a plurality of cache tags, block valid bits and sub-block valid bits are stored. The number of cache tags and block valid bits is equivalent to the number of blocks in the cache memory, and the number of sub-block valid bits is equal to the number of sub-blocks. The cache tags are stored in a cache tag random access memory (RAM).

Abstract: Circuitry for performing high speed operations on certain Boolean raster operations in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The circuitry includes a logic circuit for determining whether a particular Boolean raster operation is one for which the high speed operation is available. A Boolean raster operation is determined to be available for high speed operation if the outcome of the operation can be determined by reading only one operand, namely the source data. If the other operand, namely the destination data, is needed to determine the outcome if the operation, then the operation is performed normally. Otherwise, the operation may be performed by reading the source data only.

Abstract: A mulitplexor implementation of circuitry for performing Boolean raster operation in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The invented circuitry includes a plane raster-op select circuit and Boolean raster-op circuit. The plane raster-op select circuit selects a Boolean raster operation to be performed for each plane of graphics information as a function of foreground and background color control signals. The selected Boolean raster operation for each plane is then input to set of mulitplexors and the selected Boolean raster operation is performed on the control inputs to the multiplexors which combines source and destination data for each plane according to the selected Boolean operation for that plane.

Abstract: A method and apparatus for performing anti-aliasing of rendered lines, text and images displayed by a workstation on a video display. The anti-aliasing is performed by logically dividing each addressable frame buffer pixel into sixteen sub-pixels and generating a gray scale value for the displayed pixel that is a function of the number of sub-pixels crossed by a portion of a rendered image. The invented circuitry is part of the circuitry used for combining source and destination data which forms the displayed image namely, an anti-aliasing mask and filter, adder/subtractor logic, saturation logic and anti-aliasing logic.