Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

Abstract: A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.

Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

Abstract: A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.

Abstract: An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.

Abstract: An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.