Abstract: The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.

Abstract: A transistor that includes a biasing circuit that biases a substrate of the transistor to a positive voltage when the transistor is on, and to a negative voltage when the transistor is off. The transistor comprises a barrier semiconductor layer and a channel semiconductor layer immediately beneath the barrier semiconductor layer to form a heterojunction interface with the barrier semiconductor layer, the heterojunction inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer. A semiconductor substrate is beneath and rigidly coupled to the channel semiconductor layer and the barrier semiconductor layer. A substrate contact layer is disposed immediately beneath the semiconductor substrate. The substrate contact layer is electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact.

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

Abstract: A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.

Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

Abstract: A bidirectional switch for use in high power electronics, being compact and having low on-resistance. The bidirectional switch includes several layers epitaxially grown on a substrate, the epitaxial layer comprising a channel layer and a barrier layer grown on the channel layer, an interface of the barrier layer and the channel layer defining a heterojunction that induces a two-dimensional electron gas (2DEG) within the channel layer, the 2DEG extending laterally at the interface between the barrier and channel layers. The bidirectional switch includes two source contacts, which are ohmic, each in contact with the 2DEG channel layer, but near opposite ends of the 2DEG. The bidirectional switch further includes two gate electrodes disposed over the barrier layer and between the two source contacts. Voltages applied to these gate electrodes controls the current flow in the bidirectional switch between the two contacts.

Abstract: A package for multiple integrated circuit dies (e.g., chips). Various common couplers are layered between the chips and package contacts of the package. Each of the chips has a planar surface (e.g., a flat top surface) along which the chips include die contacts. The common couplers lie along the planar surface of each of the chips, and electrically connects the die contacts of the chips to the package contacts of the package. This allows the chips, the common couplers, and the package contacts to be stacked together to form a relatively thin, compact package. The common couplers connect the die contacts of any particular type to the corresponding package contacts of that particular type, such that the die contacts need not have the same layout as the package contacts, thus allowing packages with the same package contact layouts to be used to package chips with varying die contact layouts.

Abstract: A monolithic implementation of an integrated circuit that includes a power transistor and a biasing circuit for biasing the substrate of the power transistor. For example, the integrated circuit comprises a semiconductor substrate; and an epitaxial stack epitaxially grown on the semiconductor substrate. A power transistor uses a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. Furthermore, a biasing circuit includes circuit elements that use a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. The biasing circuit is configured to bias a portion of the semiconductor substrate beneath the power transistor.

Abstract: A transistor structure that includes a biased substrate. The transistor structure comprises a barrier semiconductor layer and a channel semiconductor layer immediately beneath the barrier semiconductor layer to form a heterojunction interface with the barrier semiconductor layer, the heterojunction inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer. A semiconductor substrate is beneath and rigidly coupled to the channel semiconductor layer and the barrier semiconductor layer. A substrate contact layer is disposed immediately beneath the semiconductor substrate. The substrate contact layer is electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact. A biasing circuit is configured to bias the substrate contact layer.

Abstract: An HEMT that includes a hybrid gate contact comprising an enhancement gate portion and a depletion gate portion. The depletion gate portion acts as a buffer that reduces the large electric field peak that would have otherwise existed at the enhancement gate portion if there was no depletion gate portion. Instead, the large electric field peak is split into two smaller electric field peaks; the first smaller electric field peak being at the drain contact side of the depletion gate portion, and the second smaller electric field peak being at the drain contact side of the enhancement gate portion. The use of this hybrid gate contact allows for greater ability to regulate and reduce electric field peaks, thus allowing the overall size of the HEMT to be reduced, and/or allowing the HEMT to handle higher voltages and currents, as compared to an HEMT with only an enhancement gate.

Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

Abstract: A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

Abstract: The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.