Patents by Inventor Thomas WOLLER
Thomas WOLLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10579388Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.Type: GrantFiled: July 19, 2018Date of Patent: March 3, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip J. Rogers, Ralph Clay Taylor, Thomas Woller
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Patent number: 10242420Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.Type: GrantFiled: November 28, 2016Date of Patent: March 26, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clayton Taylor, Michael Mantor, Kevin John McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas Woller
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Publication number: 20180321946Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip J. Rogers, Ralph Clay Taylor, Thomas Woller
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Publication number: 20170076421Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clayton Taylor, Michael Mantor, Kevin John McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas Woller
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Patent number: 9507632Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.Type: GrantFiled: November 4, 2011Date of Patent: November 29, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip Rogers, Thomas Woller
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Patent number: 8797332Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: GrantFiled: December 14, 2011Date of Patent: August 5, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Patent number: 8719543Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: GrantFiled: December 29, 2009Date of Patent: May 6, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Patryk Kaminski, Thomas Woller, Keith Lowery, Erich Boleyn
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Publication number: 20130155077Abstract: A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott HARTOG, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip J. Rogers, Ralph Clay Taylor, Thomas Woller
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Publication number: 20130147816Abstract: Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas Woller, Kevin McGrath, Rex McCrary, Philip J. Rogers, Mark Leather
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Publication number: 20130141447Abstract: A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
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Publication number: 20130135327Abstract: Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Nuwan Jayasena, Mark Leather, Michael Mantor, Rex McCrary, Kevin McGrath, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
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Publication number: 20120200576Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.Type: ApplicationFiled: November 4, 2011Publication date: August 9, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas Woller
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Publication number: 20120198458Abstract: Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device.Type: ApplicationFiled: November 30, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Nuwan S. Jayasena, Kevin McGrath, Philip j. Rogers, Thomas Woller
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Publication number: 20120188259Abstract: Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device.Type: ApplicationFiled: November 23, 2011Publication date: July 26, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip Rogers, Mark Leather
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Publication number: 20120162234Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: ApplicationFiled: December 14, 2011Publication date: June 28, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Publication number: 20110161620Abstract: Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Patryk KAMINSKI, Thomas WOLLER, Keith LOWERY, Erich BOLEYN
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Publication number: 20110161619Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Patryk KAMINSKI, Thomas WOLLER, Keith LOWERY, Erich BOLEYN
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Patent number: 5256236Abstract: A method of making a crowned cushion element is provided. The method includes the steps of forming a foam pan of a bottom and side walls of foam pieces, positioning foam slabs therein in which at least one of the slabs has a greater relaxed height than the side walls, and then adhering a top onto the foam slabs to form the cushion. The slabs are positioned within the foam pan in such a manner that they remain separated from one another when under normal compression by a user seated on the cushion. Also, the at least one slab having the greater relaxed height than the side walls also has a relaxed height greater than the width of the slab along a direction transverse to the elongate direction on either the face of the slab in contact with the top piece or the face in contact with the bottom piece of the cushion element.Type: GrantFiled: March 15, 1993Date of Patent: October 26, 1993Assignee: Baker, Knapp & Tubbs, Inc.Inventor: Thomas A. Woller
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Patent number: 4930173Abstract: An internal cushion element is constructed in the form of a box. It has a top wall, bottom wall, and side walls to define an internal cavity. A plurality of spaced vertical foam spacer slabs are positioned in the cavity extending from the front of the box to the back of the box, and from the bottom of the box to the top of the box. The strips are spaced apart in generally parallel rows. The relaxed state height of at least some of the strips is higher than that of the outside walls. Thus, the internal strips provide a crown to the cushion element. A convoluted foam patch is also provided on the outside of the cushion element.Type: GrantFiled: July 3, 1989Date of Patent: June 5, 1990Assignee: Baker, Knapp & Tubbs, Inc.Inventor: Thomas A. Woller