Abstract: A microelectronic assembly is disclosed comprising an interconnect structure having a first plurality of conductive features with a large pitch and a second plurality of conductive features with a small pitch. A first element is hybrid bonded to a first side of the interconnect structure having a first contact pad directly bonded to a conductive feature of the second plurality of conductive features. A second element is hybrid bonded to the first side of the interconnect structure with a second contact pad directly bonded to a conductive feature of the interconnect structure and electrically connected to the first contact pad. In some embodiments, the electrical connection between the first contact pad and the second contact pad is through a conductive trace disposed in the interconnect structure. In some embodiments, the electrical connection is via a bridge die hybrid bonded to a second side of the interconnect structure.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces.

Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Embodiments herein provide for probe cards and methods related thereto. A probe card comprises a probe and a substrate. The probe comprises a probe stand, a probe beam, and a probe tip. The probe tip and probe stand extend in a first direction, and the probe beam extends in a second direction different than the first direction. The substrate comprises a conductive feature disposed in a material layer. The probe stand of the probe is directly bonded to the conductive feature of the substrate via direct metal bonds.

Abstract: Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

Abstract: An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.

Abstract: A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

Abstract: Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

Abstract: Embodiments herein provide for an integrated cooling assembly comprising a semiconductor device and a heat pipe. The heat pipe comprises a non-metal material attached to a backside of the semiconductor device, or a metal material attached to a backside of the semiconductor device via a flexible material structure. The heat pipe comprises a shell defining a heat pipe chamber. The shell having an inner surface and an outer surface, and the inner surface of the heat pipe chamber includes a wick material.

Abstract: An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.

Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: A device package includes an integrated cooling assembly. The integrated cooling assembly includes a semiconductor portion and a metal cold plate attached to the semiconductor portion. The semiconductor portion includes a semiconductor device. The metal cold plate includes a base surface spaced apart from the semiconductor device to collectively define a coolant channel therebetween. The metal cold plate further includes a side wall extending downwardly from the base surface to define a perimeter of the coolant channel. The metal cold plate further includes cavity dividers extending downwardly from the base surface towards the semiconductor device.

Abstract: A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

Abstract: A display device comprises a first substrate and a second substrate. The first substrate includes a plurality of singulated control devices embedded in a first dielectric layer. The second substrate includes a plurality of singulated LEDs embedded in a second dielectric layer. The second substrate is directly bonded to the first substrate without an intervening adhesive.