Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.

Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Abstract: A device and method for protecting and installing a fire protection sprinkler. The protective and installation device has two discrete protective members coupled to one another about the sprinkler by a releasable locking arrangement defined by a connection between the two discrete protective members. At least one of the members includes a torque assist portion for applying torque to the fire protection sprinkler and each of the members includes a deflector protection portion.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.

Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

Abstract: A tandem OLED device is formed by patterning a first side of a substrate to form a first OLED opening, forming a first material layer stack in the first OLED opening, the first material layer stack comprising a first charge generation layer (CGL) and a second CGL disposed on the first CGL. After forming the first CGL and the second CGL, a second side of the substrate, opposite the first side, is patterned to form a second OLED opening in registration with the first OLED opening. A second material layer stack is formed in the second OLED opening.

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Abstract: A method of repairing a bonded structure is disclosed. The method can include debonding from a carrier a first semiconductor element that is bonded to a bonding site of the carrier, cleaning the bonding site of the carrier; and bonding a second semiconductor element to the bonding site of the carrier. The bonding can also include directly bonding the second semiconductor element and the carrier. The method can further include reducing the dielectric bond energy via a surface modification between the first semiconductor element and the carrier. Debonding the bonded structure can include delivering a fluid from one or more nozzles to a bonding interface between the first semiconductor element and the carrier to reduce the bond energy. A temperature adjustment pad can also be included to debond the bonded structure.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Bonded structures and methods of forming a bonded structure are disclosed. A bonded structure can include a first element and a second element. The first element includes a first non-conductive field region and a first conductive feature. The second element includes a second non-conductive field region and a second conductive feature. The second element is directly bonded to the first element along a bonding interface such that the first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive, and the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive. A first portion of the first non-conductive field region at the bonding interface has a first surface roughness and a second portion of the first non-conductive field region at the bonding interface has a second surface roughness. The second surface roughness can be different from the first surface roughness.

Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces.

Abstract: Bonded structures and methods of direct hybrid bonding are disclosed. Non-conductive regions of two elements, such as dies or wafers, are first bonded together to form a bonded structure. Aligned conductive regions of the bonded structure, such as metal pads or traces, are then annealed to expand and bridge a gap between them. The anneal includes rapid thermal processing (RTP), such as with radiant heating. The bond interface between the first and second conductive features includes rapid growth structure(s) indicative of the inclusion of RTP in the anneal. Additional non-RTP anneal phases can also be employed.

Abstract: A bonded structure for debugging integrated circuit devices and a method for debugging integrated circuit devices is disclosed. The bonded structure may comprise a debugging element and an integrated circuit device. The debugging element may comprise a debugging circuitry. The debugging element may be bonded to an integrated circuit device. The debugging element may be configured to debug the integrated circuit device.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

Abstract: A method for forming a bonded structure is disclosed. The method can include providing a first element having a first non-conductive region and a first conductive feature, providing a second element having a second non-conductive region and a second conductive feature, bonding the first non-conductive region to the second non-conductive region, and imparting mechanical stress to at least one of the first conductive feature and the second conductive feature. When bonding the first non-conductive region to the second non-conductive region, the first conductive feature and the second conductive feature are spaced apart by a gap. Imparting mechanical stress to the at least one of the first conductive feature and the second conductive feature reduces the gap between the first and second conductive features. The method can include annealing the first and second elements while imparting the mechanical stress to the at least one of the first conductive feature and the second conductive feature.