Abstract: Disclosed herein are methods of forming a stack of microelectronic elements. In some implementations, the method includes directly bonding a first microelectronic element to a host surface at a first bond interface to form an initial bonded structure, inspecting the first bond interface for bonding defects, initially annealing the initial bonded structure if no critical bonding defect is detected, directly bonding a second microelectronic element over the first microelectronic element after initially annealing to form a stack, and annealing the stack. The method further includes debonding the first microelectronic element from the first bond interface if at least one or more bonding defects are detected, and cleaning the host surface after the first microelectronic element has been debonded. The method further includes repeating a stacking of microelectronic elements until a desired number of microelectronic elements are stacked together.

Abstract: Bonded structures and methods of direct hybrid bonding are disclosed. Non-conductive regions of two elements, such as dies or wafers, are first bonded together to form a bonded structure. Aligned conductive regions of the bonded structure, such as metal pads or traces, are then annealed to expand and bridge a gap between them. The anneal includes rapid thermal processing (RTP), such as with radiant heating. The bond interface between the first and second conductive features includes rapid growth structure(s) indicative of the inclusion of RTP in the anneal. Additional non-RTP anneal phases can also be employed.

Abstract: A method for forming a bonded structure is disclosed. The method can include providing a first element having a first non-conductive region and a first conductive feature, providing a second element having a second non-conductive region and a second conductive feature, bonding the first non-conductive region to the second non-conductive region, and imparting mechanical stress to at least one of the first conductive feature and the second conductive feature. When bonding the first non-conductive region to the second non-conductive region, the first conductive feature and the second conductive feature are spaced apart by a gap. Imparting mechanical stress to the at least one of the first conductive feature and the second conductive feature reduces the gap between the first and second conductive features. The method can include annealing the first and second elements while imparting the mechanical stress to the at least one of the first conductive feature and the second conductive feature.

Abstract: Bonded structures and methods of direct hybrid bonding are disclosed. Non-conductive regions of two elements, such as dies or wafers, are first bonded together to form a bonded structure. Aligned conductive regions of the bonded structure, such as metal pads or traces, are then annealed to expand and bridge a gap between them. The anneal includes rapid thermal processing (RTP), such as with radiant heating. The bond interface between the first and second conductive features includes rapid growth structure(s) indicative of the inclusion of RTP in the anneal. Additional non-RTP anneal phases can also be employed.

Abstract: An integrated cooling assembly comprises a semiconductor device and a device stack disposed in a side-by-side arrangement and a cold plate bonded to both the semiconductor device and the device stack. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device and the device stack, an inlet opening, and an outlet opening. The top portion, the sidewalls, the divider, and the backside of the semiconductor device and the device stack collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening, and a channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in the same direction.

Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus includes a vacuum plate and a die ejector. The die ejector is disposed in an ejector opening of the vacuum plate. The die ejector comprises a resilient member and a plurality of pins disposed below the resilient member, where at least a portion of the die ejector is movable in a lateral direction relative to the upper surface of the vacuum plate.

Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

Abstract: Embodiments herein provide for methods of manufacturing device packages using one or more carriers. In some embodiments, a carrier configured to support a singulated device in a die pocket region includes a carrier plate with a first surface and an opposite second surface, and one or more sidewalls that define an opening extending from the first surface towards the second surface. The one or more sidewalls comprise one or more protuberances that collectively determine at least a portion of a boundary of the die pocket region. Some of the protuberances include a die supporting surface that extends beneath the die pocket region. In some embodiments, a method includes cleaning surfaces of a die disposed in a carrier. In some embodiments, a method includes engaging one or more alignment features of a first and second carrier and inverting the carriers to transfer the dies from one carrier to the other carrier.

Abstract: Embodiments herein provide for device packages with embedded cooling assemblies. A device package comprises a package substrate comprising a support surface, a device mounted on the support surface, a cold plate body comprising a first side adjacent to the device and a opposite second side, a manifold attached to the second side, and a package cover disposed over the manifold. The cold plate body and the manifold define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold.

Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

Abstract: A microelectronic assembly is disclosed comprising an interconnect structure having a first plurality of conductive features with a large pitch and a second plurality of conductive features with a small pitch. A first element is hybrid bonded to a first side of the interconnect structure having a first contact pad directly bonded to a conductive feature of the second plurality of conductive features. A second element is hybrid bonded to the first side of the interconnect structure with a second contact pad directly bonded to a conductive feature of the interconnect structure and electrically connected to the first contact pad. In some embodiments, the electrical connection between the first contact pad and the second contact pad is through a conductive trace disposed in the interconnect structure. In some embodiments, the electrical connection is via a bridge die hybrid bonded to a second side of the interconnect structure.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces.

Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Embodiments herein provide for probe cards and methods related thereto. A probe card comprises a probe and a substrate. The probe comprises a probe stand, a probe beam, and a probe tip. The probe tip and probe stand extend in a first direction, and the probe beam extends in a second direction different than the first direction. The substrate comprises a conductive feature disposed in a material layer. The probe stand of the probe is directly bonded to the conductive feature of the substrate via direct metal bonds.

Abstract: Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.