Patents by Inventor Thomas Workman

Thomas Workman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260247905
    Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus includes a vacuum plate and a die ejector. The die ejector is disposed in an ejector opening of the vacuum plate. The die ejector comprises a resilient member and a plurality of pins disposed below the resilient member, where at least a portion of the die ejector is movable in a lateral direction relative to the upper surface of the vacuum plate.
    Type: Application
    Filed: April 10, 2026
    Publication date: August 20, 2026
    Inventors: Cyprian Emeka Uzoh, Thomas Workman, Gabriel Z. Guevara
  • Patent number: 12713983
    Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: August 18, 2026
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Gaius Gillman Fountain, Jr., Guilian Gao, Jeremy Alfred Theil, Gabriel Z. Guevara, Kyong-Mo Bang, Laura Wills Mirkarimi
  • Publication number: 20260239922
    Abstract: Embodiments herein provide for methods of manufacturing device packages using one or more carriers. In some embodiments, a carrier configured to support a singulated device in a die pocket region includes a carrier plate with a first surface and an opposite second surface, and one or more sidewalls that define an opening extending from the first surface towards the second surface. The one or more sidewalls comprise one or more protuberances that collectively determine at least a portion of a boundary of the die pocket region. Some of the protuberances include a die supporting surface that extends beneath the die pocket region. In some embodiments, a method includes cleaning surfaces of a die disposed in a carrier. In some embodiments, a method includes engaging one or more alignment features of a first and second carrier and inverting the carriers to transfer the dies from one carrier to the other carrier.
    Type: Application
    Filed: April 3, 2026
    Publication date: August 13, 2026
    Inventors: Cyprian Emeka Uzoh, Aaron Todd Francis, Gabriel Guevara, Thomas Workman, Dominik Suwito
  • Publication number: 20260215268
    Abstract: Embodiments herein provide for device packages with embedded cooling assemblies. A device package comprises a package substrate comprising a support surface, a device mounted on the support surface, a cold plate body comprising a first side adjacent to the device and a opposite second side, a manifold attached to the second side, and a package cover disposed over the manifold. The cold plate body and the manifold define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold.
    Type: Application
    Filed: December 17, 2025
    Publication date: July 23, 2026
    Inventors: Belgacem Haba, Thomas Workman, Cyprian Emeka Uzoh, Guilian Gao, Rajesh Katkar
  • Publication number: 20260215265
    Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.
    Type: Application
    Filed: December 18, 2025
    Publication date: July 23, 2026
    Inventors: Rajesh Katkar, Ron Zhang, Guilian Gao, Thomas Workman
  • Publication number: 20260198394
    Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.
    Type: Application
    Filed: December 18, 2025
    Publication date: July 9, 2026
    Inventors: Cyprian Emeka Uzoh, Thomas Workman
  • Publication number: 20260144168
    Abstract: A microelectronic assembly is disclosed comprising an interconnect structure having a first plurality of conductive features with a large pitch and a second plurality of conductive features with a small pitch. A first element is hybrid bonded to a first side of the interconnect structure having a first contact pad directly bonded to a conductive feature of the second plurality of conductive features. A second element is hybrid bonded to the first side of the interconnect structure with a second contact pad directly bonded to a conductive feature of the interconnect structure and electrically connected to the first contact pad. In some embodiments, the electrical connection between the first contact pad and the second contact pad is through a conductive trace disposed in the interconnect structure. In some embodiments, the electrical connection is via a bridge die hybrid bonded to a second side of the interconnect structure.
    Type: Application
    Filed: December 23, 2024
    Publication date: May 21, 2026
    Inventors: Guilian Gao, Belgacem Haba, Cyprian Emeka Uzoh, Thomas Workman
  • Publication number: 20260136566
    Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.
    Type: Application
    Filed: December 19, 2025
    Publication date: May 14, 2026
    Inventors: Gabriel Z. Guevara, Belgacem Haba, Cyprian Emeka Uzoh, Thomas Workman
  • Publication number: 20260130217
    Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 7, 2026
    Inventors: Rajesh Katkar, Ron Zhang, Guilian Gao, Thomas Workman
  • Patent number: 12622222
    Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: May 5, 2026
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Aaron Todd Francis, Gabriel Guevara, Thomas Workman, Dominik Suwito
  • Patent number: 12622207
    Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: May 5, 2026
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Thomas Workman, Gabriel Z. Guevara
  • Patent number: 12563749
    Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 24, 2026
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
    Inventors: Gabriel Z. Guevara, Belgacem Haba, Cyprian Emeka Uzoh, Thomas Workman
  • Publication number: 20260050009
    Abstract: Embodiments herein provide for probe cards and methods related thereto. A probe card comprises a probe and a substrate. The probe comprises a probe stand, a probe beam, and a probe tip. The probe tip and probe stand extend in a first direction, and the probe beam extends in a second direction different than the first direction. The substrate comprises a conductive feature disposed in a material layer. The probe stand of the probe is directly bonded to the conductive feature of the substrate via direct metal bonds.
    Type: Application
    Filed: November 26, 2024
    Publication date: February 19, 2026
    Inventors: Belgacem Haba, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Thomas Workman
  • Publication number: 20260047472
    Abstract: Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 12, 2026
    Inventors: Oliver ZHAO, Thomas WORKMAN, Guilian GAO, Gaius Gillman FOUNTAIN, JR.
  • Patent number: 12550799
    Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 10, 2026
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Thomas Workman
  • Patent number: 12532432
    Abstract: An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: January 20, 2026
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Ron Zhang, Gaius Gillman Fountain, Jr., Thomas Workman, Belgacem Haba
  • Publication number: 20260018490
    Abstract: A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.
    Type: Application
    Filed: June 20, 2025
    Publication date: January 15, 2026
    Inventors: Belgacem Haba, Rajesh Katkar, Ron Zhang, Thomas Workman, Gaius Gillman Fountain, Jr.
  • Publication number: 20250391794
    Abstract: Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.
    Type: Application
    Filed: December 20, 2024
    Publication date: December 25, 2025
    Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, JR., Thomas Workman, Guilian Gao
  • Publication number: 20250309044
    Abstract: Embodiments herein provide for an integrated cooling assembly comprising a semiconductor device and a heat pipe. The heat pipe comprises a non-metal material attached to a backside of the semiconductor device, or a metal material attached to a backside of the semiconductor device via a flexible material structure. The heat pipe comprises a shell defining a heat pipe chamber. The shell having an inner surface and an outer surface, and the inner surface of the heat pipe chamber includes a wick material.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 2, 2025
    Inventors: Laura Wills Mirkarimi, Rajesh Katkar, Cyprian Emeka Uzoh, Thomas Workman, Suhail Jaan Sadiq
  • Publication number: 20250311149
    Abstract: An integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls and a divider extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening; and an outlet opening. The top portion, the sidewalls, the divider and the backside of the semiconductor device collectively define a first coolant channel and a second coolant channel extending laterally between the inlet opening and the outlet opening. A channel width of the first coolant channel in a direction parallel to the backside of the semiconductor device is greater than a channel width of the second coolant channel in in the same direction; and a portion of the first coolant channel is disposed above a hotspot region of the semiconductor device.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 2, 2025
    Inventors: Ron Zhang, Gaius Gillman Fountain, JR., Thomas Workman, Belgacem Haba