Patents by Inventor Thomas Workman

Thomas Workman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226290
    Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.
    Type: Application
    Filed: November 20, 2024
    Publication date: July 10, 2025
    Inventors: Belgacem Haba, Thomas Workman, Cyprian Emeka Uzoh, Guilian Gao, Rajesh Katkar
  • Publication number: 20250221128
    Abstract: A display device comprises a first substrate and a second substrate. The first substrate includes a plurality of singulated control devices embedded in a first dielectric layer. The second substrate includes a plurality of singulated LEDs embedded in a second dielectric layer. The second substrate is directly bonded to the first substrate without an intervening adhesive.
    Type: Application
    Filed: October 29, 2024
    Publication date: July 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Publication number: 20250210459
    Abstract: A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.
    Type: Application
    Filed: August 1, 2024
    Publication date: June 26, 2025
    Inventors: Belgacem Haba, Rajesh Katkar, Ron Zhang, Thomas Workman, Gaius Gillman Fountain, JR.
  • Publication number: 20250212554
    Abstract: A method of transferring a plurality of individual elements including providing a plurality of singulated elements on a stretchable tape, stretching the stretchable tape to increase separation between the singulated elements and forming a reconstituted wafer with at least one of the plurality of elements.
    Type: Application
    Filed: June 17, 2024
    Publication date: June 26, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Patent number: 12341083
    Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: June 24, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Gaius Gillman Fountain, Jr., Thomas Workman, Kyong-Mo Bang, Ron Zhang
  • Patent number: 12330749
    Abstract: The present disclosure relates generally to the field of facilitating a laminar flow and sound mitigation between a wetted hull of a vessel and surrounding fluid. More specifically, the present disclosure includes methods, systems, and apparatuses to facilitate providing and sustaining a laminar flow of a fluid across a vessel. A system for sustaining laminar flow of a fluid across a vessel comprising a main control unit. The main control unit comprises one or more air compressor units configured to generate air. An integrated longitudinal air distribution assembly is secured to a wetted hull of the vessel. The distribution assembly comprises a series of air dispersal modules configured to distribute the generated air across the wetted hull of the vessel to create at least one air layer between the wetted hull of the vessel and the fluid to sustain the laminar flow of the fluid across the vessel.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: June 17, 2025
    Assignee: Parker Maritime Technologies, LLC
    Inventors: William J. Parker, III, Harold Thomas Workman, Katherine Howell Brinson
  • Publication number: 20250146754
    Abstract: A thermal treatment reactor for feedstocks and method of use. The thermal treatment reactor comprises an infeed assembly, a furnace, a rotary drum, a discharge assembly, and a liberator assembly. The rotary drum may comprise forwarding flights, mixing flights, oscillating flights, and raking pins. The feedstock to be thermally treated enters the reactor through the infeed assembly. The feedstock is fed into the reactor in a controlled manner by means of a screw conveyor system. The thermally-treated product exits the reactor via the discharge assembly, which separates the thermally treated product into a VOC liberator, from whence the product enters into a cooling system to reduce the temperature for safe storage and handling.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: Omega Holdings LLC
    Inventors: Bijoy Thomas, Nathan Coltrane, Ronald Hoover, Thomas Workman, Chad Johnson
  • Patent number: 12272677
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: April 8, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Publication number: 20250079364
    Abstract: A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.
    Type: Application
    Filed: October 30, 2023
    Publication date: March 6, 2025
    Inventors: Cyprian Emeka Uzoh, Oliver Zhao, Gabriel Z. Guevara, Dominik Suwito, Gaius Gillman Fountain, Jr., Rajesh Katkar, Thomas Workman
  • Publication number: 20250054837
    Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 13, 2025
    Inventors: Thomas Workman, Ron Zhang, Kyong-Mo Bang, Belgacem Haba, Gaius Gillman Fountain, JR.
  • Patent number: 12191233
    Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Belgacem Haba, Thomas Workman, Cyprian Emeka Uzoh, Guilian Gao, Rajesh Katkar
  • Publication number: 20250006520
    Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.
    Type: Application
    Filed: August 29, 2023
    Publication date: January 2, 2025
    Inventors: Cyprian Emeka Uzoh, Thomas Workman, Gabriel Z. Guevara
  • Publication number: 20250006689
    Abstract: Disclosed is a bonded structure including a substrate that includes a surface and at least one bumper extending above the surface by a bumper height. The bonded structure further includes at least one die directly bonded to the surface adjacent the bumper.
    Type: Application
    Filed: November 17, 2023
    Publication date: January 2, 2025
    Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, JR., Thomas Workman, Guilian Gao, Laura Wills Mirkarimi
  • Publication number: 20240387439
    Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Belgacem Haba, Laura Wills Mirkarimi, Javier A. DeLaCruz, Rajesh Katkar, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Publication number: 20240334733
    Abstract: A tandem OLED device is formed by patterning a first side of a substrate to form a first OLED opening, forming a first material layer stack in the first OLED opening, the first material layer stack comprising a first charge generation layer (CGL) and a second CGL disposed on the first CGL. After forming the first CGL and the second CGL, a second side of the substrate, opposite the first side, is patterned to form a second OLED opening in registration with the first OLED opening. A second material layer stack is formed in the second OLED opening.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Oliver Zhao, Cyprian Emeka Uzoh, Thomas Workman, Guilian Gao
  • Patent number: 12080672
    Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 3, 2024
    Assignee: ADEIA Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Laura Wills Mirkarimi, Javier A. DeLaCruz, Rajesh Katkar, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Publication number: 20240266255
    Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
    Type: Application
    Filed: December 28, 2023
    Publication date: August 8, 2024
    Inventors: Belgacem HABA, Gaius Gillman FOUNTAIN, JR., Thomas WORKMAN, Kyong-Mo BANG, Ron ZHANG
  • Publication number: 20240222319
    Abstract: A method of repairing a bonded structure is disclosed. The method can include debonding from a carrier a first semiconductor element that is bonded to a bonding site of the carrier, cleaning the bonding site of the carrier; and bonding a second semiconductor element to the bonding site of the carrier. The bonding can also include directly bonding the second semiconductor element and the carrier. The method can further include reducing the dielectric bond energy via a surface modification between the first semiconductor element and the carrier. Debonding the bonded structure can include delivering a fluid from one or more nozzles to a bonding interface between the first semiconductor element and the carrier to reduce the bond energy. A temperature adjustment pad can also be included to debond the bonded structure.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 4, 2024
    Inventors: Guilian GAO, Laura Wills MIRKARIMI, Gabriel Z. GUEVARA, Thomas WORKMAN, Dominik SUWITO
  • Publication number: 20240203948
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 20, 2024
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, JR., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11955463
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 9, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe