Patents by Inventor Thomas WUEBBEN
Thomas WUEBBEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10837120Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.Type: GrantFiled: March 26, 2020Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Patent number: 10724149Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: GrantFiled: March 29, 2019Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Publication number: 20200224326Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Applicant: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Patent number: 10665705Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.Type: GrantFiled: February 28, 2019Date of Patent: May 26, 2020Assignee: Infineon Technologies AGInventors: Thomas Wuebben, Peter Irsigler, Hans-Joachim Schulze
-
Patent number: 10607839Abstract: A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.Type: GrantFiled: June 28, 2017Date of Patent: March 31, 2020Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Peter Irsigler, Thomas Wuebben
-
Publication number: 20190249330Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: ApplicationFiled: March 29, 2019Publication date: August 15, 2019Applicant: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Publication number: 20190198650Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.Type: ApplicationFiled: February 28, 2019Publication date: June 27, 2019Applicant: Infineon Technologies AGInventors: Thomas WUEBBEN, Peter IRSIGLER, Hans-Joachim SCHULZE
-
Patent number: 10273597Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: GrantFiled: June 29, 2017Date of Patent: April 30, 2019Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Patent number: 10263101Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.Type: GrantFiled: October 17, 2016Date of Patent: April 16, 2019Assignee: Infineon Technologies AGInventors: Thomas Wuebben, Peter Irsigler, Hans-Joachim Schulze
-
Publication number: 20180005831Abstract: A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.Type: ApplicationFiled: June 28, 2017Publication date: January 4, 2018Inventors: Hans-Joachim Schulze, Peter Irsigler, Thomas Wuebben
-
Publication number: 20180002826Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: ApplicationFiled: June 29, 2017Publication date: January 4, 2018Applicant: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
-
Publication number: 20170117395Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.Type: ApplicationFiled: October 17, 2016Publication date: April 27, 2017Applicant: Infineon Technologies AGInventors: Thomas WUEBBEN, Peter IRSIGLER, Hans-Joachim SCHULZE