Patents by Inventor Thomas Y. Ho
Thomas Y. Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7436196Abstract: A system that determines power consumption on an IC chip. The system includes a test structure located within the IC chip variations which includes one or more gates which receives power from a power source, wherein each gate has a different drive strength, and wherein the output of each gate is coupled to a load through a corresponding switch. The system also includes a current-measuring mechanism coupled to the power supply which measures the current consumed by the gates. When a specific switch is activated, the output of a corresponding gate is coupled to the load, thereby causing the corresponding gate to drive the load. The current consumed by the corresponding gate is measured by the current measuring mechanism. The measured current can be used to determine the power consumption of the corresponding gate driving the load.Type: GrantFiled: February 15, 2006Date of Patent: October 14, 2008Assignee: Apple Inc.Inventors: William C. Athas, Herbert Lopez-Aguado, Thomas Y. Ho
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Patent number: 7167181Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.Type: GrantFiled: June 9, 2003Date of Patent: January 23, 2007Assignee: Apple Computer, Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
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Publication number: 20040130552Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.Type: ApplicationFiled: June 9, 2003Publication date: July 8, 2004Inventors: Jerome F. Duluk, Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
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Patent number: 6717576Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.Type: GrantFiled: August 20, 1999Date of Patent: April 6, 2004Assignee: Apple Computer, Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
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Patent number: 6671747Abstract: A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores the original order is provided. Several alternative approaches for implementing the RIFO control mechanisms for write efficiency and correctness. Method for use in conjunction with a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by the write instructions to at least one hardware device coupled to the host processor for receiving the symbols from the host processor, where the method preserves a predetermined order in which the symbols are received by the hardware device.Type: GrantFiled: August 3, 2000Date of Patent: December 30, 2003Assignee: Apple Computer, Inc.Inventors: Jack Benkual, Thomas Y. Ho, Jerome F. Duluk, Jr.
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Patent number: 6597363Abstract: Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.Type: GrantFiled: August 20, 1999Date of Patent: July 22, 2003Assignee: Apple Computer, Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck
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Patent number: 6268875Abstract: Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.Type: GrantFiled: August 4, 2000Date of Patent: July 31, 2001Assignee: Apple Computer, Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck
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Patent number: 6229553Abstract: Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.Type: GrantFiled: August 20, 1999Date of Patent: May 8, 2001Assignee: Apple Computer, Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck
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Patent number: 5570051Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.Type: GrantFiled: May 31, 1995Date of Patent: October 29, 1996Assignee: Xilinx, Inc.Inventors: David Chiang, Napoleon W. Lee, Thomas Y. Ho, Nicholas Kucharewski, Jr.
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Patent number: 5565792Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.Type: GrantFiled: September 6, 1994Date of Patent: October 15, 1996Assignee: Xilinx, Inc.Inventors: David Chiang, Napoleon W. Lee, Thomas Y. Ho, David A. Harrison, Nicholas Kucharewski, Jr., Jeffrey H. Seltzer
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Patent number: 5357153Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.Type: GrantFiled: January 28, 1993Date of Patent: October 18, 1994Assignee: Xilinx, Inc.Inventors: David Chiang, Napoleon W. Lee, Thomas Y. Ho, David A. Harrison, Nicholas Kucharewski, Jr., Jeffrey H. Seltzer
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Patent number: 5349249Abstract: More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.Type: GrantFiled: April 7, 1993Date of Patent: September 20, 1994Assignee: Xilinx, Inc.Inventors: David Chiang, Thomas Y. Ho, Wei-Yi Ku, George H. Simmons, Robert W. Barker
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Patent number: 5302866Abstract: An input block for PLDs programmable logic devices) has a flip-flop including a master latch and a slave latch, a pad for inputting data, configuration bits, and a global clock input signal for clocking the input data to the flip-flop means. The flip-flop is controlled by the configuration bits so as to function alternatively as a register, a latch or transparently. The input block further includes at least one clock enable signal input terminal and logic elements responding to the configuration bits for providing the clock enable signal for the register function as well as the latch function of the flip-flop.Type: GrantFiled: March 18, 1993Date of Patent: April 12, 1994Assignee: Xilinx, Inc.Inventors: David Chiang, Thomas Y. Ho, Jeffrey H. Seltzer, Jeffrey Goldberg