Patents by Inventor Thomas Yan

Thomas Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200281804
    Abstract: The invention relates to a massage insole driven by intelligent sensing motor which includes a structurally symmetrical left insole and right insole. The left insole and the right insole each includes a massaging mechanism for massaging the sole of the foot, and a receiving pad body for receiving the massaging mechanism and a control mechanism. The control mechanism is arranged in the receiving pad body. The massaging mechanism includes a massage bead chain, a driving component for driving the massage bead chain to rotate, a reset component for driving the massage bead chain to be reset. Two ends of massage bead chain are respectively sleeved on the driving component and the reset component. The control mechanism includes a control chip, a timing component and a thermostatic component. The driving component, the timing component and the thermostat component are electrically connected to the control chip.
    Type: Application
    Filed: April 16, 2019
    Publication date: September 10, 2020
    Inventor: King Tong Thomas YAN
  • Patent number: 9595323
    Abstract: A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at the selected word line voltage node based on the received current and the estimated resistance so that a voltage of the word line comb substantially equals a reference voltage.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 14, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Yingchang Chen, Jeffrey Koonyee Lee, Chang Siau, Anurag Nigam, Thomas Yan
  • Patent number: 8861258
    Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 14, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Zhida Lan, Roy E Scheuerlein, Thomas Yan
  • Publication number: 20140233299
    Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Zhida Lan, Roy E. Scheuerlein, Thomas Yan
  • Patent number: 8442075
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Patent number: 8320196
    Abstract: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 27, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Thomas Yan, Luca Fasoli, Roy E Scheuerlein
  • Publication number: 20120002476
    Abstract: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
    Type: Application
    Filed: September 15, 2011
    Publication date: January 5, 2012
    Inventors: Thomas Yan, Luca Fasoli, Roy E. Scheuerlein
  • Patent number: 8050109
    Abstract: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: November 1, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Thomas Yan, Luca Fasoli, Roy E Scheuerlein
  • Patent number: 7991020
    Abstract: An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth the output data rate, and provides main data and equalization data at one fourth the output data rate to at least one four-to-one multiplexer. The main data and equalization data is multiplexed onto an output node at the output data rate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Jun Cai, Matt Dayley
  • Publication number: 20110170584
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Patent number: 7936789
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Publication number: 20110032774
    Abstract: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 10, 2011
    Inventors: Thomas Yan, Luca Fasoli, Roy E. Scheuerlein
  • Publication number: 20070230515
    Abstract: An integrated circuit provides equalized outputs. Main data and equalization data is produced at one fourth of the output data rate, and multiplexed onto an output node at the output data rate.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Hing (Thomas) Yan To, Jun Cai, Matt Dayley